Introduction: This diagram illustrates an external interrupt line or external event line. A diagonal line is drawn on the signal line, and the number 19 is marked next to it, indicating that there are 19 such lines. The blue dashed arrows in the diagram mark the transmission path of the external interrupt signal.
First, the external signal enters from chip pin number 1, passes through edge detection circuit number 2, enters interrupt suspend request register through OR gate number 3, and finally outputs to NVIC interrupt detection circuit through AND gate number 4. This edge detection circuit is controlled by rising edge or falling edge selection register. Users can use these two registers to control which edge is needed to generate an interrupt. Because the selection of rising edge or falling edge is controlled by two parallel registers, users can select rising edge or falling edge at the same time. However, if only one register controls it, only one edge can be selected.
Next is OR gate number 3. The other input of this OR gate is the software interrupt/event register. From this, we can see that the software can request an interrupt or event before external signals. That is, when the corresponding bit of the software interrupt/event register is "1", the OR gate number 3 will output a valid signal regardless of the external signal.
An interrupt or event request signal enters the suspend request register after passing through OR gate number 3. Up to this point, the signal transmission paths for interrupts and events are consistent, meaning that the suspend request register records the level changes of external signals.
The external request signal finally passes through AND gate number 4 to send an interrupt request to the NVIC interrupt controller. If the corresponding bit in the interrupt mask register is "0", the request signal cannot be transmitted to the other end of the AND gate, thus achieving interrupt masking.
Understanding the external interrupt request mechanism makes it easy to understand the event request mechanism. The red dashed arrow in the diagram indicates the transmission path of the external event signal. The external request signal passes through the OR gate (number 3) and then enters the AND gate (number 5). This AND gate functions similarly to the AND gate (number 4), introducing control from the event mask register. Finally, a transition signal from the pulse generator is converted into a single pulse and output to other functional modules in the chip. From this diagram, we can also see that, from the perspective of external stimulus signals, the sources of interrupts and events can be the same. The reason for dividing them into two parts is that interrupts require CPU involvement and software interrupt service functions to complete the result after the interrupt; however, events are generated by a pulse generator, and the hardware automatically completes the result of the event. Of course, the corresponding linkage components need to be set up beforehand, such as triggering DMA operations or AD conversions.
For a simple example: an external I/O triggers an AD conversion to measure the weight of an external object. If a traditional interrupt channel is used, the I/O trigger needs to generate an external interrupt, the external interrupt service routine starts the AD conversion, and the interrupt service routine submits the final result after the AD conversion is completed. If an event channel is used, the I/O trigger generates an event, which then triggers the AD conversion, and the interrupt service routine submits the final result after the AD conversion is completed. In comparison, the latter does not require software involvement in AD triggering and has a faster response speed. If an event-triggered DMA operation is used, certain linked tasks can be completed without any software involvement.
In summary, the event mechanism can be simply viewed as providing a fully automated hardware-driven process from triggering to generating results, without software intervention. This reduces CPU load, saves interrupt resources, and improves response speed (hardware is always faster than software). It is an effective method to leverage hardware to enhance the CPU chip's event processing capabilities.
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