Electronic engineers are senior engineering and technical personnel who engage in research, teaching, product design, technological development, production, and management of various electronic devices and information systems. They are generally divided into hardware engineers and software engineers.
Hardware engineers are primarily responsible for circuit analysis and design; they use computer software to design PCBs and then test and debug them after the PCBs are manufactured and electronic components are soldered in the factory.
Software engineers are primarily responsible for writing and debugging embedded programs for microcontrollers, DSPs, ARMs, FPGAs, etc. FPGA programming sometimes falls under the scope of hardware engineers' work.
Summary of 20 common design mistakes
Error 1
The value of these pull-up/pull-down resistors doesn't matter much, so just choose an integer like 5K.
Commentary: A 5K resistor value does not exist on the market. The closest is 4.99K (1% accuracy), followed by 5.1K (5% accuracy). Their costs are 4 times and 2 times higher than the 4.7K resistor with 20% accuracy, respectively. Resistors with 20% accuracy only have a few values: 1, 1.5, 2.2, 3.3, 4.7, and 6.8 (multiples of 10). Similarly, capacitors with 20% accuracy also only have these values. Choosing other values necessitates higher accuracy, multiplying the cost several times over without any benefit.
Error 2
There shouldn't be any problems with this part of the circuit as long as the software is designed this way.
Commentary: Many electrical characteristics of hardware are directly controlled by software, but software is prone to unexpected problems; once a program malfunctions, its actions are unpredictable. Designers should ensure that regardless of the software's actions, the hardware should not suffer permanent damage within a short period.
Error 3
This logic can be built using 74XX gate circuits, but that's too basic. Let's use a CPLD instead; it looks much more sophisticated.
Commentary: The gate circuits of a 74XX series only cost a few cents, while a CPLD costs at least tens of dollars. Not only does this increase the cost many times over, but it also adds several times more work to production, documentation, and other tasks.
Error 4
The PCB design requirements for this board are not high, so just use thinner traces and let it be automatically routed.
Commentary: Automated routing inevitably occupies a larger PCB area and generates many times more vias than manual routing. For products with large production volumes, PCB manufacturers consider factors other than business factors when lowering prices, such as trace width and the number of vias. These factors affect the PCB yield and the number of drill bits consumed, respectively. Saving costs for suppliers provides a reason for price reductions.
Error 5
Our system is powered by 220V, so we don't need to worry about power consumption.
Commentary: Low-power design is not just about saving electricity; its greater benefits include reduced costs for power modules and cooling systems, as well as reduced electromagnetic radiation and thermal noise interference due to lower current. As device temperature decreases, device lifespan increases accordingly (for semiconductor devices, lifespan is halved for every 10-degree increase in operating temperature).
Error 6
I feel more at ease using resistors to pull up these bus signals.
Commentary: There are many reasons why signals need to be pulled up or down, but not every reason requires it. Pulling up or down a simple input signal with a resistor draws less than tens of microamps, but pulling up a driven signal can draw milliamps. Modern systems often have 32-bit address and data bits, and may also have 244/245 isolated buses and other signals. Pulling up all of them would consume several watts of power in these resistors (don't treat these few watts of power consumption with the mindset of 80 cents per kilowatt-hour).
Error 7
What should we do with these unused I/O ports of the CPU and FPGA? Let's leave them idle for now and deal with them later.
Commentary: If unused I/O ports are left floating, even a small amount of external interference can cause them to oscillate repeatedly as input signals. The power consumption of MOS devices is primarily determined by the number of gate flips. Pulling them up will also result in microamps of current flowing through each pin. Therefore, the best approach is to set them as outputs (provided that no other signals with driving capabilities are connected externally).
Error 8
This FPGA still has so many gates left that we can use them all; feel free to explore its potential.
Commentary: The power consumption of an FPGA is directly proportional to the number of flip-flops used and their toggling frequency. Therefore, the power consumption of the same FPGA model can vary by a factor of 100 at different circuits and at different times. Minimizing the number of high-speed flip-flops is the fundamental way to reduce FPGA power consumption.
Error Nine
These small chips have very low power consumption, so we don't need to worry about them.
Commentary: It is difficult to determine the power consumption of chips with relatively simple internal structures. It is mainly determined by the current on the pins. An ABT16244 consumes less than 1 mA when there is no load, but its specification is that each pin can drive a 60 mA load (such as matching a resistor of tens of ohms). That is, the power consumption at full load can reach 60*16=960mA. Of course, with such a large power supply current, the heat will fall on the load.
Error 10
With so many control signals for the memory, my board only needs to use the OE and WE signals. I'll just ground the chip select, which will make the data come out much faster during read operations.
Commentary: The power consumption of most memory chips is more than 100 times greater when chip select is active (regardless of OE and WE) than when chip select is inactive. Therefore, CS should be used to control the chip as much as possible, and the width of the chip select pulse should be shortened as much as possible while meeting other requirements.
Error 11
Why do all these signals have overshoot? They can be eliminated if the matching is done well.
Commentary: Except for a few specific signals (such as 100BASE-T and CML), most signals have overshoot. As long as it's not too large, matching isn't always necessary, and even if matching is used, it doesn't have to be perfect. For example, TTL output impedance is less than 50 ohms, some even as low as 20 ohms. If such a large matching resistor were used, the current would be extremely high, and the power consumption would be unacceptable. Furthermore, the signal amplitude would be unusable. Besides, the output impedance of a signal is generally not the same when it's high and low, making perfect matching impossible. Therefore, for TTL, LVDS, 422, and other signals, matching only needs to ensure the overshoot is acceptable.
Error Twelve
Reducing power consumption is a hardware-related matter, not a software-related one.
Commentary: Hardware merely sets the stage; software is the performer. Almost every chip access and signal toggle on the bus is controlled by software. If software can reduce the number of external memory accesses (by using more register variables and internal cache, etc.), respond to interrupts promptly (interrupts are often active low with pull-up resistors), and implement other specific measures for each board, it will greatly contribute to reducing power consumption.
Error Thirteen
This 100MHz CPU can only handle 70% of the workload; replacing it with a 200MHz CPU will solve the problem.
Commentary: The processing power of a system involves a variety of factors. In communication services, the bottleneck is usually the memory. No matter how fast the CPU is, it is useless if external access is not fast.
Error Fourteen
Using a larger cache for the CPU should speed things up.
Commentary: Increasing the cache size does not necessarily lead to improved system performance. In some cases, disabling the cache can be faster than using it. This is because data moved to the cache must be reused multiple times to improve system efficiency. Therefore, in communication systems, only the instruction cache is typically enabled, while the data cache, even when enabled, is limited to a portion of storage space, such as the stack. Furthermore, program design must consider both cache capacity and block size. This relates to the length of critical code loops and jump ranges. If a loop is slightly larger than the cache size and is repeatedly executed, it will cause significant performance issues.
Error 15
If one CPU can't handle the workload, use two CPUs to distribute the processing power, which can double the processing capacity.
Commentary: When it comes to moving bricks, two people should be twice as efficient as one; when it comes to drawing, having an extra person will only make things worse. The number of CPUs used should be determined after a thorough understanding of the business logic, minimizing the coordination costs between two CPUs, and ensuring that 1+1 is as close to 2 as possible, and definitely not less than 1.
Error Sixteen
This CPU has a DMA module, so it will definitely be fast to move data using it.
Commentary: True DMA involves hardware preempting the bus and simultaneously starting both devices, reading from one end and writing from the other within a single cycle. However, many DMA systems embedded in the CPU are merely simulations. Before each DMA operation, considerable preparation work is required (setting the starting address and length, etc.). During the transfer, data is often first read into the chip's temporary storage and then written out, meaning each data transfer requires two clock cycles. While this is faster than software-based transfers (no instruction fetching, no loop jumps, or other extra work), if only a few bytes are being transferred at a time, the extensive preparation work and function calls involved make the process inefficient. Therefore, this type of DMA is only suitable for large data blocks.
Error 17
To ensure a clean power supply, the more decoupling capacitors the better.
Commentary: Generally speaking, more decoupling capacitors will make the power supply more stable, but too many also have disadvantages: wasted cost, difficult wiring, and excessive power-on inrush current. The key to decoupling capacitor design is to choose the right capacitance and place it in the right location. Most chip datasheets provide design guidelines for decoupling capacitors, and it is best to follow the datasheet.
Error 18
If a user makes a mistake and causes a problem, it's not my fault.
Commentary: It's correct to require users to strictly follow the manual, but users are human and make mistakes. It's unacceptable for a single wrong key press to cause a system crash or a wrong plug to burn out the circuit board. Therefore, protection against various user errors is essential.
Error 19
The reason this board is broken is that the board on the other end has a problem, it's not my responsibility.
Commentary: Sufficient compatibility should be maintained with all external hardware interfaces. You shouldn't shut down simply because the other party's signal is abnormal. An abnormal signal should only affect the relevant functionalities, while other functions should continue to work normally. It shouldn't completely stop working or even permanently damage the interface, and you should be able to restore normal operation immediately once the interface is restored.
Error 20
Our system has such high requirements that all chips, including MEM, CPU, and FPGA, must be the fastest.
Commentary: In a high-speed system, not every part operates at high speed. Moreover, the price of a device roughly doubles with each increase in speed, and it also has a significant negative impact on signal integrity.
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