The core idea of ​​boundary scan technology is to insert a boundary scan unit between the core logic and I/O pins inside the device. This unit is "transparent" during normal chip operation and does not affect the normal operation of the circuit board. Each boundary scan unit is connected serially to form a scan chain. The test vector is input serially through the scan input terminal, and the corresponding pin states are set to load the test vector. The system's test response is output serially through the scan output terminal for data analysis and processing, completing fault diagnosis and location of the circuit system. A schematic diagram of the boundary scan test principle is shown in Figure 1. [IMG=Schematic diagram of basic principle of boundary scan test]/uploadpic/THESIS/2007/12/2007121410332950026E.jpg[/IMG] Figure 1 Schematic diagram of basic principle of boundary scan test. The physical basis of boundary scan test is the IEEE 1149.1 boundary scan test bus and the boundary scan structure designed within the device. The standard boundary scan structure is shown in Figure 2. The boundary scan test bus consists of five signal lines: Test Data Input (TDI), Test Data Output (TDO), Test Clock (TCK), Test Mode Select (TMS), and Reset Signal (TRST). The standard boundary scan architecture adds a boundary scan unit (BSC) to the core logic I/O pins within the device, along with instruction registers, data registers, and the Test Access Port (TAP) controller related to boundary scan testing. During testing, the boundary scan architecture can operate on either the data register or the instruction register; that is, it can shift the test vector into the boundary scan unit from the TDI port and shift the test response out from the TDO port. [IMG=Standard Boundary Scan Structure]/uploadpic/THESIS/2007/12/2007121410333752146Y.jpg[/IMG] Figure 2 Overall Design Scheme of Standard Boundary Scan Structure The portable boundary scan fault diagnostic instrument needs to generate boundary scan test vectors based on the description file of the circuit under test, then convert them into IEEE1149.1 boundary scan test bus signals and automatically load them into the system under test. Simultaneously, it automatically reads the boundary scan test response from the TDI pin for analysis and processing, makes fault diagnosis decisions and location isolation based on the boundary scan corresponding algorithm, and finally displays the diagnostic results on the LCD. This paper adopts an on-chip programmable system solution to co-design the portable fault diagnostic instrument on a single FPGA, optimizing the designed circuit system in terms of scale, reliability, size, power consumption, time-to-market, development cost, product maintenance, and hardware upgrades (the overall structure diagram is shown in Figure 3). [IMG=Portable Boundary Scan Fault Diagnostic Instrument Circuit Structure Diagram]/uploadpic/THESIS/2007/12/2007121410334398981W.jpg[/IMG] Figure 3 Portable Boundary Scan Fault Diagnostic Instrument Circuit Structure Diagram Hardware Design This paper uses an Altera FPGA with an embedded soft-core Nios processor as the carrier to implement the SOPC system of the boundary scan fault diagnostic instrument. The boundary scan fault diagnostic instrument mainly realizes the functions of boundary scan test vector generation, JTAG bus signal generator, boundary scan fault diagnosis application software, fault display, etc., and is the core of the portable boundary scan fault diagnosis system. The Nios soft-core CPU is created and parameterized using SOPC Builder. Simultaneously, an SOPC system integrating memory, timers, LCD interface components, and IEEE1149.1 test bus user logic is constructed. The internal module configuration diagram of the on-chip programmable system for boundary scan fault diagnosis is shown in Figure 4. [IMG=Figure 4 Internal Module Configuration Diagram of Boundary Scan Fault Diagnosis SOPC System]/uploadpic/THESIS/2007/12/20071214103350481643.jpg[/IMG] Figure 4 Internal Module Configuration Diagram of Boundary Scan Fault Diagnosis SOPC System This article utilizes a wizard-style interface to flexibly customize the boundary scan fault diagnosis system, employing a standard Nios II soft-core processor with an added 4KB instruction cache. Furthermore, to facilitate debugging the hardware and software of the boundary scan fault diagnosis system, a JTAG debugging unit is added to the processor module. Once the SOPC system hardware and software are successfully debugged and can run independently, the JTAG debugging unit can be removed.