Abstract: This paper introduces a solution for high-speed data acquisition using a CPLD-controlled OV7110 image sensor, providing a PC peripheral for image reading. The system built according to this method has been experimentally verified to perform well. Keywords: CPLD; CMOS image sensor; high-speed acquisition system; OV7110 In the current image sensor market, CMOS sensors are increasingly favored by consumers due to their low price. Currently, most applications use software for data reading, but this undoubtedly wastes instruction cycles, and for high-speed devices, software reading presents certain difficulties in program design and timing coordination. Therefore, to acquire large amounts of image signals, this paper designs an image acquisition system based on a CPLD, achieving high-speed reading of the OV7110 CMOS image sensor, with a reading rate of up to 8 Mb/s. 1. Hardware Circuit Scheme Figure 1 shows the block diagram of the high-speed data acquisition system based on the CPLD-controlled OV7110 CMOS image sensor. It mainly consists of two parts: the OV7110 parameter setting circuit and the image sampling circuit. 1.1 Parameter Setting Circuit of OV7110 After power-on, the CMOS sampling chip needs to be initialized to determine its operating mode, window size, scanning method, output data format, etc. These parameters are set through the SCCB interface on the OV7110 chip. SCCB is a bidirectional three-wire synchronous serial bus developed by OmnVision, with an enable line SCCB_E, a clock line SIO_C, and a data line SIO_D. SCCB_E is active low; if grounded, SIO_C and SIO_D operate very similarly to the I2C bus. The OV7110's operating mode, window size, scanning method, and output data format can all be set through the corresponding registers. In this system, the AT89C51 is used as the master device, and the OV7110 is used as the slave device. The P1.2 and P1.3 ports of the AT89C51 are used to simulate the SCCB bus in software, and its parameters are written into the corresponding internal registers. Similar to the I2C bus, in the SCCB bus, after the master device sends a byte, the slave device needs to pull the data line SIO_D low as an acknowledge signal (ACK) back to the master device to indicate successful transmission. It is worth noting that because CMOS devices can only withstand very low sink current, the pull-up resistors connected to the clock line SIO_C and the data line SIO_D should be between 3 and 5 kΩ. Furthermore, after the master device AT89C51 finishes sending parameters, it must immediately release the data line SIO_D to ensure it is in a floating state. That is, after sending a byte, the AT89C51 immediately executes an instruction to cause the data line SIO_D to issue a read signal. 1.2 Image Sampling Circuit The system is set to black and white mode, with a maximum resolution of 640×480. The data output waveform of the CMOS chip is shown in Figure 2 (this figure is only a schematic diagram for ease of analysis). In the figure, VSYNC is the vertical field synchronization signal, and its falling edge indicates the start of a frame. HSYNC is the horizontal line synchronization signal, and its rising edge indicates the start of a line signal. HREF is the horizontal window pixel clock signal, i.e., the data output synchronization clock signal. Its falling edge updates data, and the rising edge represents a stable period where data can be read. The data is output line by line. Y represents the image grayscale data. The following describes how the CPLD controls the data reading of the CMOS chip. First, the VSYNC and CHSYNC signals are checked sequentially for validity. It is important to prevent interference from glitches. Since glitches are very short, a flag is used in this design. After a valid edge is detected (rising edge for VSYNC, falling edge for CHSYNC), the signal is checked again after a certain time to see if it is still valid. If valid, the signal is correct. The source code is as follows: Since pixel data is output according to the PCLK clock, the enable signal RCE, write signal RWE, read signal RRE, and address signal ADDRESS for the RAM used to store the image are all generated by the CPLD. The read signal RRE is set to "1" during CPLD write operations. Since the PCLK rising edge signal is stable during data output, and RAM writes data on the rising edge of WR, PCLK can be used as the write signal RWE after HREF is valid (HREF=1). A binary counter is designed to count PCLK on the falling edge after HREF is valid, and its output is used as the RAM address signal ADDRESS. Thus, the address signal is updated on the falling edge of PCLK, and data is stored on the rising edge. The source code is as follows: Setting the write signal RWE to RAM: Since the number of image pixels is known, i.e., the number of data points is known, the CPLD sends a count completion signal R after counting is complete. Simultaneously, the RAM address line ADDRESS and the read/write signals RWE and RRE are switched to the address lines and read/write signals WR and RD of the AT89C51. After receiving the stop signal R, the AT89C51 begins reading data from the RAM and uploads it to the PC via the RS232 serial port. It is important to note that the RAM address space reaches 512 KB, while the microcontroller's maximum addressable space is only 64 KB. Therefore, page-based reading is used when reading RAM, reading 64 KB at a time. This involves extracting three lines from port P1 as the highest three bits of the RAM address, which, together with ports P0 and P2, form the address lines of the AT89C51. 2. Conclusion The method of using a CPLD to acquire data from a CMOS image sensor transforms the active CMOS device into a controllable form, enabling high-speed data reading from the CMOS image sensor. The system built using this method has shown good performance in experimental results. This signal reading method can also be applied in many other situations requiring high-speed image data acquisition.