Introduction USB, serial ports, and parallel ports are common interfaces for communication between PCs and peripherals. However, for images with large data volumes, the speed of data acquisition using the serial RS-232 protocol is insufficient to meet the requirements of image data acquisition. While USB data acquisition can meet the required speed, it requires peripherals to support the USB protocol, and the interface between the USB protocol and commonly used engineering software is not yet widespread, causing difficulties in use. Some users attempt to use the standard parallel port (SPP) for data acquisition, but the 150kb/s transmission rate of the SPP protocol is also too low for image data acquisition. Therefore, to acquire large amounts of image data, this paper adopts the Enhanced Parallel Port Protocol (EPP) with a higher transmission rate and an FPGA to achieve high-speed data acquisition from the OV7620 CMOS image sensor, with a maximum rate of 2Mb/s. Hardware Circuit Scheme Figure 1 shows the block diagram of a high-speed data acquisition system for the OV7620 CMOS image sensor based on FPGA and EPP technology. It mainly consists of three parts: the OV7620 parameter configuration circuit, the image sampling circuit, and the PC data reading circuit. Figure 1 System Block Diagram OV7620 Parameter Configuration Circuit After power-on, the system needs to initialize the CMOS image acquisition chip to determine the window position, window size, and color or black-and-white working mode of the acquired image. These parameters are configured through the SCCB interface provided on the OV7620 chip. The SCCB interface uses a simple, bidirectional two-wire synchronous serial bus I2C, with SCL and SDA pins. Since the 89C2051 does not have a standard I2C bus interface, an I2C bus can be simulated using software. The OV7620 window position and size, black-and-white and color modes, and scanning method can all be set through the corresponding registers. These registers are all readable and writable. The specific operation method is as follows: Page writing can be used. During register writing, first send the write enable instruction OX42, then send the destination register address, followed by the data to be written. After writing to a register, the CMOS automatically increments the register address, and the program can continue writing without needing to input the address again. Reading registers follows the same process, except the instruction is changed to OX43. The I2C bus function is entirely implemented by the levels on the SCL and SDA lines and their interaction. The I2C bus protocol specifies the following conditions: Start-up timing: When SCL is high, a falling edge appears on SDA; Transmission timing: After the start-up condition is met, SDA is in a stable data state, SCL generates a positive pulse, and one bit of data is transmitted; Acknowledgment timing: When the slave receives a complete data byte, with the master releasing SDA, the master outputs a positive clock pulse to SCL, and the slave pulls SDA low to acknowledge; Stop condition: When SCL is high, a rising edge appears on SDA. This condition can solve the problem of multi-machine contention, that is, when two devices are communicating, the insertion of a third party will terminate the data communication of the former. Its main feature is that each bit of each device judges the state of the bus. The start and stop conditions of the I2C bus are shown in Figure 2. Figure 2: Start and stop conditions of the I2C bus. Image sampling circuit In tunnel parallelism, non-destructive testing, and perpendicularity measurement instruments, a 320×320 image resolution is commonly used. Black and white mode can basically meet the requirements of image recognition for image feature points. Therefore, the sampling parameters of this system are set to an image resolution of 320×320, black and white mode, and ZV image format. The output waveform of the CMOS image chip in ZV port format is shown in Figure 3. In the figure, VSYNC is the vertical field synchronization signal, and its falling edge indicates the start of a frame of image (CMOS acquires images column by column). HREF is the horizontal field synchronization signal, and its rising edge indicates the start of a column of image data. PCLK is the output data synchronization signal, and Y is the image grayscale information. The following describes how the FPGA samples data from the image sensor. Figure 3 OV7620 output timing in ZV port format. To perform speed matching, there are two handshake signals between the FPGA and the PC: READY and ACK. They coordinate the FPGA's read and write process to the same data storage chip. READY is the signal from the FPGA to the PC that the image data has been read; ACK is the signal from the PC to the FPGA that the data has been read. Both are active low. During data sampling, pulling READY high indicates that data acquisition is in progress. At this time, the FPGA generates the image MEM_WR (write signal) and ADDRESS (address) based on the OV7620's VSYNC, HREF, and PCLK signals, and reads the OV7620's data into the cache. When the next VSYNC signal arrives, it indicates that one frame of data has been acquired. The FPGA then sends a READY request signal to the PC, indicating that image acquisition is complete. If the PC does not provide an ACK signal, the FPGA starts sampling the next frame of data and placing it in the cache, overwriting the existing data. If the PC responds, the FPGA stops sampling data. The PC reads data through the parallel port's EPP mode. The timing diagram for reading in EPP mode is shown in Figure 4. In read mode, nWRITE (EPP write signal) remains high. When nDATASTB (EPP read signal) goes low, it prepares to read peripheral data. Once the peripheral data is ready, nWAIT (peripheral busy flag) is set high. At this time, the PC program performs an I/O read operation (nDATASTB signal) to the port at base address +4 (EPP data port). On the rising edge of the nDATASTB read pulse signal, the PC reads data from the data bus. The entire process is completed within one ISA cycle. Figure 4 shows the read timing in EPP mode. Figure 5 shows the timing of the FPGA implementing the EPP protocol. The PC continuously checks if the READY signal is valid. Only when READY is valid can the PC read image data. At the same time, ACK is set high, indicating that the PC is reading image data from the data buffer. At this point, the FPGA stops acquiring images (and does not generate a write signal). The FPGA detects the PC sending a read pulse (CPU_DS) through the EPP, generating a cache MEM_RD (read signal) and an address. It reads a byte from the cache and places it on the parallel port, simultaneously sending a BUSY signal to the PC. The PC can then read one byte of data, completing the entire data read/write process. During the data reading process, the PC_WRITE (write signal) on the EPP port must remain high. Figure 5 shows the timing diagram of the FPGA implementation of the EPP protocol. Conclusion: The FPGA-based high-speed CMOS data acquisition method can make the active CMOS devices controllable through the FPGA, allowing the PC to indirectly perform addressing operations on the memory. In this system, high-speed acquisition and processing of CMOS signals was implemented using the PC's parallel port. The system, built using the aforementioned hardware and software methods, achieved a stable sampling rate of 15 frames/s. This system has been applied in a pipeline non-destructive testing prototype with good results. This signal acquisition method can also be applied in many other situations requiring high-speed image data acquisition.