For most people in the control industry and microcontroller enthusiasts, PLC and PLD are familiar terms. But do you understand the subtle difference between them? If you're interested, please read on for today's introduction.
1. A Programmable Logic Controller (PLC) is a member of the computer family, designed and manufactured for industrial control applications. Early PLCs were called Programmable Logic Controllers, or PLCs for short, and were primarily used to replace relays to achieve logic control. With technological advancements, the functionality of this device has far exceeded the scope of logic control; therefore, today this device is called a Programmable Logic Controller, or PC for short. However, to avoid confusion with the abbreviation for Personal Computer, the abbreviation PLC (Programmable Logic Controller) is still used.
The primary characteristics of a PLC
High reliability, abundant I/O interface modules, modular structure, simple and easy-to-learn programming, easy installation, and convenient maintenance.
Functions of PLC
Logic control, time-based control, counting control, step (sequence) control
PID control
Data control: PLC has data processing capabilities.
Communication and networking
Other: PLCs also have many special function modules suitable for various special control requirements, such as positioning control modules and CRT modules.
2. PLD is short for Programmable Logic Device, and FPGA is short for Field Programmable Gate Array. The two have the same function, but their implementation principles are slightly different. Therefore, we can sometimes ignore the difference between the two and refer to them as Programmable Logic Device or PLD/FPGA.
PLD is one of the most dynamic and promising technologies in the field of electronic design, and its impact is no less than that of the invention and application of microcontrollers in the 1970s. What can PLD do? It is no exaggeration to say that PLD can perform the functions of any digital device, from high-performance CPUs to simple 74 circuits.
A PLD is like a blank sheet of paper or a pile of building blocks. Engineers can freely design a digital system using traditional schematic input methods or hardware description languages. Through software simulation, we can verify the correctness of the design beforehand. After the PCB is completed, the PLD's online modification capability can be used to modify the design at any time without changing the hardware circuitry. Using PLDs to develop digital circuits can significantly shorten design time, reduce PCB area, and improve system reliability.
A typical PLD consists of an AND gate and an OR gate array. Any combinational logic can be described by an AND-OR expression. Therefore, a PLD can complete a large number of combinational logic functions in a product-sum manner. The products at this stage are mainly PAL (Programmable Array Logic) and GAL (General Purpose Array Logic).
Regarding programmable logic devices (PLDs), designers can rapidly develop, simulate, and test their designs using inexpensive software tools. The designs can then be quickly programmed into the devices and immediately tested in actual operating circuits. The PLDs used in the prototypes are identical to those used in the final production devices (such as network routers, DSL modems, DVD players, or car navigation systems). This eliminates NRE (Network Execution Environment) costs, and the final design is completed much faster than when using custom fixed logic devices.
Another key advantage of using PLDs is that customers can modify the circuitry during the design phase until they are satisfied with the design. This is because PLDs are based on rewritable memory technology—to change the design, only a simple reprogramming of the devices is required. Once the design is complete, customers can immediately put it into production, simply by using the final software design file to program the required number of PLDs.
The programming principle of PLD will be introduced below using FPGA as an example.
The programming data storage units are distributed in an array within the FPGA, as shown in the diagram below. Each storage unit is a 5-transistor SRAM structure, requiring only one bit line. The T-transistor is the control gate for that unit, controlled by the word line. Data is serially shifted into the shift register, which sequentially selects a word line of the storage unit. When a column of word lines is high, the T-transistor of that column of storage units is turned on, connecting to the bit line. Under the control of the write signal, the data of one word in the data shift register is written to that column of storage units via the bit lines.
Programming data is loaded into the FPGA according to a specific data structure and format. The programming data stream is automatically generated by the development software. The development software converts the design into a netlist file. It automatically partitions, places, and routes the logic circuits and verifies the FPGA design. Then, it generates the programming data stream in PROM format and forms a programming data file. Finally, it can store the programming data file in the PROM.
Programmable data storage unit array structure
Currently, any PLD device exceeding a certain integration level (e.g., 1000 gates or more) is generally referred to as a CPLD. A CPLD consists of programmable logic function blocks surrounding a programmable interconnect matrix. Interconnection between logic units is achieved using fixed-length metal wires, and the number and functionality of I/O control modules are increased. The basic structure of a CPLD can be considered as consisting of three parts: a programmable logic array (LAB), programmable I/O control modules, and programmable internal interconnects (PIA).
1) Programmable Logic Array (LAB) A programmable logic array is composed of several programmable logic macrocells (LMCs). The LMC mainly includes AND arrays, OR arrays, programmable flip-flops and multiplexers, which can be configured to operate in sequential or combinational modes.
1) In the macrocells of a CPLD, if there are many AND terms in the output expression and the corresponding OR gate inputs are insufficient, other OR gates in the same unit (or other units) can be combined with it using programmable switches, or unused product terms in each macrocell can be provided to other macrocells for use.
(2) Multi-Flip-Flop Structure: In the early stages, each output macrocell (OLMC) of a programmable device only had one flip-flop, while a CPLD macrocell typically contains two or more flip-flops. Only one of these flip-flops is connected to the output terminal, while the outputs of the remaining flip-flops are not connected to the output terminal but can be reflected in the AND array through appropriate buffer circuits, thus forming a more complex sequential circuit with other flip-flops. These internal flip-flops not connected to the output terminal are called "buried" flip-flops. This structure increases internal resources without increasing the number of pins.
(3) Asynchronous Clocks: Early programmable devices could only implement synchronous sequential circuits. In CPLD devices, the clocks of each flip-flop can operate asynchronously. In some devices, the clocks of the flip-flops can also be selected through a data selector or clock network. In addition, the asynchronous clearing and asynchronous setting of flip-flops in OLMC can also be controlled by product terms, thus making the application more flexible.
2) Programmable I/O Unit (IOC)
The I/O cell (Input/Output Cell, IOC) of a CPLD is the interface between internal signals and I/O pins. The structure varies depending on the device and its function. Because array-type devices typically only have a few dedicated input terminals, with most ports being I/O terminals, and system input signals generally require latching, I/O is often handled as a separate unit.
3) Programmable Internal Connectivity (PIA)
The function of programmable interconnects is to provide an interconnect network between logic macrocells and between logic macrocells and I/O units. Each logic macrocell receives signals from its inputs via the programmable interconnect array and sends the macrocell's signals to their destination. This interconnect mechanism is highly flexible, allowing changes to the internal layout without affecting pin assignments.
In summary, the biggest difference between the two lies in their control logic. A PLC uses fixed logic (its functions are implemented through software modifications), while a PLD uses variable logic (its functions are implemented through modifications to its internal circuit structure). Furthermore, PLCs are generally used in applications requiring fault-driven high-voltage circuitry (automation professionals will be very familiar with this), such as the control of large machine tools and robotic arms. PLDs, on the other hand, are primarily used for early-stage integrated circuit design work, such as simulation circuits, and fault-based control.
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