Leveraging the customizability, portability, and low power consumption of embedded systems, this paper studies the data acquisition hardware circuit and data processing software of a pile measuring instrument using the reflection wave method. First, the structure affecting the performance of the pile measuring instrument is analyzed. Then, the key technologies and design framework involved in the system are introduced from both hardware and software perspectives. Finally, an improvement scheme for this design is proposed. 1 Introduction In recent years, pile dynamic testing technology based on wave stress theory has been widely used. Its basic principle is that after the pile top is impacted by a pile hammer, the integrity of the pile is analyzed based on the measured force and acceleration data at the pile top. Pile measuring instruments based on this method are lightweight, flexible, require less transportation and on-site installation work, have high measurement efficiency, short measurement time, and are less prone to safety accidents. This design utilizes embedded system technology to develop a pile measuring instrument with real-time data acquisition, data analysis, and local processing report generation functions. The instrument features automatic signal gain adjustment, high data sampling speed, automatic data storage, and a high degree of overall automation. 2. System Problem Analysis 2.1 Existing Pile Measuring Instruments The working environment for pile measuring instruments to complete data acquisition and processing is generally harsh, filled with various interferences (from both inside and outside the system). When the measured signal is very weak, the effective data will be "drowned out" by noise, resulting in large errors in data acquisition and processing, and reduced reliability. Some pile measuring instruments are equipped with acquisition systems with too narrow a frequency response range, which cannot be reflected by dynamic measurement curves when there are multiple fractures in the pile, and defects in the pile body of very shallow depths can lead to blind spots in the test. Most existing instruments use software-based programmable amplification, which reduces the sampling rate of the data acquisition system and cannot accurately reflect fast, small signals. 2.2 Solutions To address interference signals, this system first connects the signal to an analog low-pass filter in the hardware before data sampling to filter out high-frequency noise; in the early stage of data processing, a software digital filter is used to perform band-stop filtering on the introduced specific frequency noise. In the specific design, an analog active filter is added before A/D sampling for pre-filtering to limit the signal bandwidth, remove high-frequency components above 1/2 sampling frequency, and prevent spectral aliasing. The parameters of sensors, sample-and-hold circuits, and analog-to-digital converters have a significant impact on the system's frequency response range. When selecting components, the performance of each component should be weighed holistically to find the optimal balance between cost and speed. To improve measurement accuracy while minimizing the impact on measurement speed, the system adopts a fully hardware-based high-speed dynamic amplification method. 3. System Structure and Key Technologies First, functional analysis is performed to plan the system architecture and list the various component modules. Then, the detailed design of the underlying layers is carried out, and finally, the system integration is completed. A schematic diagram of the pile measuring instrument is shown in Figure 1. The pile measuring instrument includes functional modules for data acquisition, data processing (including digital filtering, analysis processing, graphical display, and report printing), and data storage. Externally, a hammer and sensors are also required. The pile measuring instrument has three signal input interfaces: a velocity sensor, an active accelerometer, and a passive accelerometer. These are selected by an analog multiplexer to enter an analog low-pass filter. The filtered signal is then split into two paths after passing through a sample-and-hold circuit. One path enters a low-precision analog-to-digital converter comparator, which monitors the signal amplitude range in real time and reports it to the control unit, which generates the corresponding amplification factor and sets the programmable amplifier. The other path first amplifies the signal through a programmable amplifier, then enters a high-precision analog-to-digital converter comparator, and finally the control unit sets the amplification factor and stores it synchronously with the amplified signal. The block diagram of the data acquisition section is shown in Figure 2. After one sampling cycle, the control unit requests an interrupt from the ARM processor. The processor reads the data information, completes the preprocessing analysis and graphical display, and transmits the data to the host computer via the USB interface to obtain complete data analysis and report printing services. The block diagram of the data processing and data storage section is shown in Figure 3. During the sampling process, the synchronization timing control of the data amplification factor and the measurement results is a key issue that the hardware needs to address. Digital filtering, data analysis calculation, and exponential amplification display are key issues that the software needs to address. 3.1 Hardware Related The entire system structure includes data acquisition, data processing, and data storage. Only some key technologies are discussed below, followed by a description of the control unit implementation. 3.1.1 Dynamic Amplification Technology Due to the large range of reflected wave amplitude variations, to achieve high resolution even for small signals, hardware automatically selects the signal amplification factor in real time, increasing the system's dynamic range. At its maximum range, a low-precision A/D conversion is performed. The control unit CPLD (Complex Programmable Logic Device) reads the converted value, encodes and stores it in a 16-bit SRAM (two IS62C256 cascaded units), and sends the gain coefficient of the current signal to the amplifier. Since the design uses two cascaded programmable amplifiers AD526 with nine gain options (1, 2, 4, 8, 16, 32, 64, 128, 256), a 10-bit or higher analog-to-digital converter is required for bipolar signals to amplify all gains. A MAX1426 10-bit analog-to-digital converter is selected as the low-precision ADC, and an AD1674 12-bit analog-to-digital converter as the high-precision ADC to reduce development costs. The block diagram of the dynamic amplification structure is shown in Figure 4. Utilizing the hardware programmability of the CPLD, the timing of data sampling, amplification, and analog-to-digital conversion is set to a pipelined manner. While the high-precision ADC is converting data, the floating-point amplifier circuit synchronously amplifies the next stage signal. While the subsequent 12-bit ADC performs analog-to-digital conversion, the preceding 10-bit ADC begins the next round of data conversion. In this design, the conversion time of the 12-bit high-precision ADC is longer than the time of the preceding amplification stage; the pipeline's time consumption is mainly in the subsequent stage. 3.1.2 Lead Trigger Technology To ensure the integrity of the sampled waveform, the system design utilizes a CPLD and SRAM to implement lead triggering, i.e., a fixed length of signal conversion data is pre-stored before triggering. The trigger level is encoded and latched digitally inside the CPLD, and compared with the digital signal converted by the low-precision ADC. When the trigger condition is met, the CPLD records the address of the current data in the SRAM and starts a timer/counter. When the counter is full, data filling into the SRAM stops, and one sampling operation is completed. 3.1.3 NandFlash Boot Process The processor selected is the S3C2410 with an ARM9 core and rich controller features. Considering the characteristics of running an embedded operating system on a processor, a 64MB Nand Flash K9F1208UOM is selected to store program code and power-loss protected data. Two 16-bit HY57V561632 chips are cascaded to form a 64MB SDRAM to store the running program code and data. The multi-stage boot process of the system is as follows: In the first stage, the processor first initializes the hardware devices and loads the second-stage running code into the SDRAM. After setting up the stack, it jumps to the entry point of the second stage. In the second stage, the hardware devices to be used are initialized first, then the system memory mapping relationship is detected, the kernel image and root file system of the operating system are loaded from the Nand Flash into the memory space of the SDRAM, the boot parameters of the kernel are set, and finally the system kernel is called to complete the boot process of the operating system. 3.2 Related Software 3.2.1 Porting of Embedded Operating System The system platform is designed based on the embedded Linux operating system, making full use of its strong real-time and portability features. Porting the operating system to adapt to this hardware platform requires writing two parts of code: one is the bootloader code mentioned above; the other is the part of the kernel code closely related to the hardware. Most of the kernel code closely related to the hardware is located in the `arch` subdirectory, while drivers for additional devices are usually located in the `drivers` subdirectory. 3.2.2 Digital Filtering Method The system employs different filtering processes for the two input signals from the velocity sensor and the accelerometer to suit their respective characteristics. For the installation resonant oscillator of the velocity sensor, appropriate digital filtering can complement it, thereby expanding the sensor's operating frequency range. Therefore, this digital filtering method is based on frequency domain analysis, with the principle of precisely filtering out the installation resonant oscillator. The appropriateness of the filtering can be verified by comparing the amplitude spectrum curves before and after filtering, selecting the frequency at the first trough to the left of the installation resonant peak as the low-pass cutoff frequency. The digital filtering for the accelerometer follows the same principle as for the velocity sensor, but its filtering process is performed after integration. 3.2.3 Display Processing, Analysis, and Testing Procedure The system first provides the raw curves of the test results to reflect the original recording state during on-site testing. However, the raw curves, without any processing, often cannot clearly reflect the integrity characteristics of the pile. Therefore, to accurately analyze the measurement results, a single raw curve is insufficient; it needs to be processed using physically meaningful methods. These processing techniques include rotation, exponential amplification, and smoothing. Another noteworthy point is that, to improve the accuracy and reliability of the time-domain analysis results, and to ensure the rationality of the processing methods used, the submitted curve can be incorporating a frequency domain curve and frequency domain analysis results. For the velocity sensor, this is the original amplitude spectrum; for the accelerometer, it should be the integral spectrum. 4. Conclusion The design scheme proposed in this paper features low cost and wide frequency response. Due to experimental limitations, the bottleneck in data acquisition speed is the conversion rate of the two analog-to-digital converters. If high-speed analog-to-digital converters are selected, and a 16-bit high-precision analog-to-digital converter is chosen, the system performance will be significantly improved.