Abstract: A flexible and simple anti-interference filter was designed using the ispLSI1032E in-circuit programmable device from Lattice. Keywords: Programmable logic device, filter, anti-interference 1. Problem Statement In synchronous serial data transmission, even a small spike on the clock line can cause data transmission errors, affecting the normal operation of the system. The traditional method is to add a small capacitor in parallel at the receiving end to filter out spikes. This method can only remove interference at a fixed frequency. In actual operation, interference may be generated by a mixture of multiple interference sources, and its frequency may vary. Furthermore, if there are multiple receiving ends in synchronous serial transmission, a capacitor needs to be added in parallel on each receiving line. This multiple capacitors connected in parallel on the same signal line will inevitably lead to signal distortion. With the development of modern electronic technology, EPLDs, with their flexible and convenient programming, have increasingly become one of the important tools in modern electronic design. This paper introduces a digital filter based on EPLD, which can suppress interference on certain low-frequency lines. This filter can block interference signals in certain frequency bands, thus achieving hardware anti-interference. Due to the use of EPLD technology, hardware programming is convenient and flexible, and corresponding measures can be taken to address the characteristics of different interference sources. 2. Solution Serial transmission lines are prone to interference during actual transmission, typically in the form of small glitches or narrow pulses. This interference can be filtered out by utilizing the different characteristics of the main signal. 2.1 Basic Working Principle Eliminating interference requires two input signals: the main signal and a reference clock signal. The reference clock signal undergoes frequency division and pulse width adjustment to create the required delay in the main signal source. This delay is then compared with the main signal itself, thereby filtering out some narrow-wave interference signals from the main signal source. The schematic diagram of the filter is shown in Figure 1. The device can be the ispLSI1032E from LATTICE, and the reference clock signal can be an 8MHz crystal oscillator. [IMG=Schematic diagram of the filter]/uploadpic/THESIS/2007/12/2007122111262385413Z.jpg[/IMG] 2.2 Specific Circuit Design The programming software is LATTICE's ispEXPERTSystem, a complete digital system design software. Design input can be done via schematic diagram, hardware description language, or mixed input. It can also perform functional and timing simulations on the designed digital circuit system. 2.2.1 Frequency Divider Circuit The frequency divider circuit can be determined based on the pulse width of each specific interference source. The specific circuit is shown in Figure 2. CLK is an 8MHz crystal oscillator signal, which, after shaping, serves as the trigger signal for the DQ flip-flop. OUT1 outputs a 4MHz square wave signal after frequency division by two, and simultaneously serves as the clock signal for the next stage flip-flop. OUT2 outputs a 2MHz square wave signal after frequency division by four. FW1 outputs a pulse signal with a frequency of 4MHz and a pulse width of 125ns, and FW2 outputs a pulse signal with a frequency of 2MHz and a pulse width of 250ns. The specific waveforms are shown in Figure 3. By analogy, cascading DQ flip-flops can output 8-fold and 16-fold frequency divider signals. The pulse width can also be changed according to the specific situation. The circuit is similar to the generation circuits of FW1 and FW2. From Figure 2, the waveform shown in Figure 3 is obtained through simulation in ispEXPERT. [IMG=Frequency divider circuit]/uploadpic/THESIS/2007/12/2007122111262914765K.jpg[/IMG] [IMG=Frequency divider circuit waveform]/uploadpic/THESIS/2007/12/2007122111264083979T.jpg[/IMG] 2.2.2 Delay circuit According to the situation of the interference source, the signal mentioned above is used as the trigger clock. The unprocessed signal source is triggered to generate a delay, and then compared with itself. In this way, some interference signals are filtered out due to the narrow pulse width. The specific circuit is shown in Figure 4. [IMG=Delay Circuit]/uploadpic/THESIS/2007/12/2007122111264674515P.jpg[/IMG] SIGNIN is the signal to be processed. After being triggered by the first flip-flop, a delay is generated, and it is simultaneously fed into the second-level flip-flop to generate a second-level delay. The frequency of the CLKIN signal can be determined according to the width of the interference source, but it should be noted that the width of the interference source must be much smaller than the width of the signal source; otherwise, the signal width will be significantly reduced, resulting in the destruction of characteristics. The circuit simulation waveform is shown in Figure 5. [IMG=Circuit Simulation Waveform]/uploadpic/THESIS/2007/12/20071221112809584276.jpg[/IMG] On the SIGNIN signal line, the second pulse is filtered out because its width is less than the CLKIN signal period. This is particularly important on the clock line of synchronous serial transmission. 3. Effect Analysis This circuit is simple and reliable. The author used this circuit to solve interference problems in a serial synchronous communication process and achieved good results. Because it is based on EPLD technology, no additional hardware is needed, and the programming is flexible, allowing direct simulation in ispEXPERT, saving a significant amount of experimental time. However, two points need attention in actual operation: First, when using this filter, the main signal pulse will have a certain delay. As a synchronization clock, this delay will not have a significant impact on serial communication, but if used on data lines or other signal lines, the impact of the delay time on the system needs to be considered. Second, when programming with ispEXPERTSystem, its macro device functions are similar to TTL devices, but some pins are different. Furthermore, the above principles can be extended to address interference on various transmission lines. Reference 1: Wang Xiaojun. A Concise Tutorial on VHDL. Beijing: Tsinghua University Press, 1997.