As mentioned in the previous issue, in the 5G era, various consumer electronics products are trending towards being lightweight, multifunctional, and low-power, and semiconductor packaging is developing towards high integration.
In order to accommodate more pins in a smaller package area, wafer-level packaging ( WLP ) is also receiving increasing attention.
What is wafer-level packaging?
Wafer-level packaging (WSP) treats the wafer as the processing object, performing CSP packaging and testing directly on the entire wafer , and finally dicing it into individual devices. It integrates more functions, is smaller in size, and can be directly mounted onto a substrate or printed circuit board.
This change allows for unified consideration of chip design and packaging design, which can simplify the supply chain, shorten production cycles, and reduce costs.
Currently, wafer-level packaging is generally divided into two types: Fan-in and Fan-out , which will be discussed in detail below.
01. Fan-in packaging
Fan-in packaging, also known as the standard WLP process, produces a packaged IC that is almost identical in size to the original die. It can be directly mounted onto a substrate or printed circuit board, significantly reducing processing costs and improving processing efficiency.
Since there is no intermediate carrier, the solder balls are directly implanted on the silicon substrate, which makes it far more sensitive than BGA . This effectively increases the bandwidth of data transmission and reduces signal loss, resulting in a significant improvement in data transmission speed and stability. At the same time, without molding compound or ceramic encapsulation, its heat dissipation capability is also stronger.
Fan-in packaging has become the mainstream packaging technology for mobile / consumer applications, offering a lower-cost solution compared to substrate-based packaging.
02. Fan-out encapsulation
Fan-out packaging is based on wafer reassembly technology. It involves re-embedding the tested and qualified chip onto the wafer and then packaging it according to steps similar to the standard WLP process. The resulting actual package area is larger than the original size of the IC die.
Since the actual package area is larger than the chip area, other active devices and passive components can be added while expanding the area, forming a SiP .
Fan-out packaging enables chiplet and heterogeneous integration and is expected to become widespread in the coming years as 5G , AI and autonomous driving develop.
Source: Semiconductor Industry Observer
Advanced packaging technology has become a must for high-performance chips, and in the foreseeable future, wafer-level packaging will replace traditional packaging technology.
As we can see from the above, the most critical difference between wafer-level packaging and traditional packaging is that after the packaged wafer is cut into pieces, it is directly mounted onto a substrate or printed circuit board, reducing the size of a single component by several times.
Mounting area of a single component under different packaging technologies
Furthermore, wafer-level packaging has smaller solder ball diameters and smaller solder ball spacing (ranging from 0.3mm to 0.5mm ), so more precise alignment and placement pressure are required during die bonding.
This means that using more flexible and better-controlled high-precision motors for operation is better suited to the mounting requirements of advanced wafer packaging.
National Olympic Linear Rotary Motor
Assistance provided
More flexible die bonding solution
The bidirectional linear actuator and soft landing enable precise force control, with a repeatability of +/- 2μm , allowing for gentler contact with the wafer surface and accurate vacuum pick-and-place.
The ±0.01N precision force control is at a world-leading level, helping to improve the flexibility of production equipment, increase production efficiency and product yield, and has applied for more than 100 related core patents, intellectual property rights and software copyrights .
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