Abstract: When transmitting messages in a CAN network, noise interference or transmission interruptions often cause errors in the messages received by the receiver. To ensure timely and reliable message transmission and effective error detection, error control is necessary. This paper details the error control principle and implementation method of Cyclic Redundancy Check (CRC) codes in the CAN bus. Keywords: Cyclic Redundancy Check, Error Control, Message In a CAN system, to ensure the correctness of message transmission, error control is required during the communication process. Currently, the commonly used method is feedback retransmission, where the transmitter automatically retransmits once an error message is received from the receiver. In this case, error control only requires error detection. Two common error detection codes are parity check codes and cyclic redundancy check codes. Parity check codes are the most common type of error detection code, with a simple implementation but poor error detection capability. Cyclic redundancy check codes are also simple to encode and have a low false positive rate, so they are widely used in communication systems. The following section introduces the principle and implementation method of cyclic redundancy check codes (CRC codes) in CAN networks. 1. Working Principle of CRC Error Detection: CRC error detection treats the bit sequence of the processed message as the coefficients of a binary polynomial A(x). These coefficients are divided by a pre-agreed generator polynomial g(x) between the sender and receiver. The remainder P(x) is then appended to the original message as a CRC checksum and sent to the receiver. The receiver divides the received message B(x) by the same g(x). If the remainder equals p(x), the transmission is error-free (A(x) and B(x) are the same). Otherwise, an error occurs during transmission, and the sender retransmits the message, restarting the CRC check until no error is found. Several points need attention during this process: ① When performing CRC calculations, a binary (modulo-2) arithmetic operation is used, meaning addition does not carry and subtraction does not borrow. Essentially, it's a logical XOR operation between two operands. ② Before performing CRC calculations, the polynomial A(x) represented by the sent message is multiplied by xn, where n is the highest power of the generator polynomial g(x). For binary multiplication, A(x)·xn is equivalent to shifting A(x) left by n bits to store the remainder p(x), so the actual transmitted message becomes A(x)·xn+p(x); ③ The coefficients of the first and last bits of the generator polynomial g(x) must be 1. Currently, several generator polynomials have been included in international standards, such as CRC-4, CRC-12, CRC-16, CCITT-16, and CRC-32. The generator polynomial used in the CAN bus is g(x) = x¹⁵ + x¹⁴ + x¹⁰ + x⁸ + x⁷ + x⁴ + x³ + 1. It can be seen that the polynomial used in the CRC check in the CAN bus can verify seven levels, which is much higher than the levels (two to five) of general CRC checks (CRC-4, CRC-12, CRC-16, etc.). Therefore, its error detection capability is very strong, and the false positive rate is extremely low, making it an effective error detection method for improving data transmission quality. 2. Circuit Implementation of CRC Code 2.1 Characteristics of the Hardware Circuit In order to generate CRC codes in the CAN bus, the hardware circuit, in addition to reset and clock signals, requires the participation of the following two control signals: ① The desestuff signal, whose effective logic value is 1; ② The enable signal for CRC verification, also with an effective logic value of 1. The characteristic of this hardware circuit is that it uses selectors and inverters instead of the XOR gates used in traditional designs, which not only achieves the comparison function but also reduces production costs and provides engineers with a new design approach. 2.2 Hardware Circuit Diagram Several points need to be explained in the diagram: ① The enable signal and desestuff signal are omitted; ② The logic value represented by crcnxt is the result of XORing the input message sequence with the highest bit of the CRC register; ③ Labels 0-14 indicate the 15-bit CRC register, triggered on the rising edge; ④ Labels 1-6 indicate the combinational logic of selectors and inverters, implementing the XOR function. The logic function of the selector is Y=AB+AC, and the specific structure is shown in Figure 3. 2.3 Circuit Operation Process From the above analysis, we can see that: ① When enable=0, the CRC is cleared to 0; ② When enable=1 and destuff=1, normal CRC calculation is performed; ③ When enable=1 and destuff=0, data transmission is paused while de-padding is being performed. When all control signals are valid, each bit of the input message is XORed with the most significant bit of the CRC register and then shifted to the least significant bit. Simultaneously, bits 13, 9, 7, 6, 3, and 2 of the register are XORed with their most significant bit, and the results are shifted left by one bit. Other register bits that have not undergone XOR operations are also shifted left by one bit until each bit of the message is shifted into the CRC register. At this point, the value in the register is the calculated CRC code. If the bit sequence length of the message is 16, then 16 left shifts are required to process each bit of the message. If Ck represents the k-th bit value of the CRC register and Ck' represents the k-th bit value after shifting (k=0,1,2,3……15), then the shifting pattern is shown in Table 1. Table 1 Shift Pattern Table 3 Software Implementation of CRC Check Code CRC checksums are very convenient to implement in software. Given that current materials mostly describe implementations using C or assembly language, and lack implementations using hardware description languages, a Verilog HDL behavioral description program for CRC codes is provided here. This program compiles successfully in Verilog_XL and has been successfully synthesized and optimized on Synopsis. //Implement CRC code using Verilog HDL module crc(clk,rst,enable,destuff,datain,crc); input clk; input rst; input enable; input destuff; input datain; output[14:0]crc; reg[14:0]crc; wire crcnxt=datain︿crc[14]; always@(posedge rst or posedge clk) begin if(rst)crc=0; else if(enable && destuff) begin if(crcnxt) crc<=crc︿15h'4599; else crc<=｛crc[13:0],1'b0｝; end end endmodule 4 Simulation Waveform Assuming that a standard format remote frame is sent, the required data bytes are 8, and the identifier sequence is 10101011000, then the waveform after simulation of the above program is shown in Figure 4. The CRC sequence is output starting from the 20th bit. CRC checksums have strong error detection capabilities, and because both software and hardware implementations of CRC error detection are simple, they are widely used in various data verification applications. CRC error detection is a powerful means to improve data transmission quality and efficiently detect errors.