1. System Design
2. Design a PLC ladder diagram program
For elevator electrical control systems using PLCs as intermediate process controllers, after the circuit schematic and wiring diagrams are designed and drawn, it is also necessary to design and draw the corresponding PLC ladder diagram program. The ladder diagram program is the logic control diagram for various soft and hard relays within the PLC . Its logic control method is similar to the logic control circuit diagram between relays in the intermediate process control, making it a crucial part of the PLC control electrical system design. When designing the ladder diagram program, one should follow the methods outlined in the PLC user manual to understand the PLC 's I/O interface allocation, combination arrangement, and codes; the codes for various soft relays, data areas, and channels; and the coding rules and codes for commonly used instructions.
The following rules should generally be followed when designing trapezoidal diagrams:
( 1 ) The normally open and normally closed contacts of I/O points and various internal soft relays can be reused multiple times.
( 2 ) The coil of the soft relay should not be directly connected to the bus on the left; there should be a transition point.
( 3 ) There should be no more contacts on the right side of the soft relay.
( 4 ) In a ladder diagram, coils with the same symbol cannot appear repeatedly. (Except for the SET and RST instructions)
( 5 ) The input and output points of the PLC can be used as soft relays.
3. Indoctrination Procedure
Once the ladder diagram is programmed, it must be loaded into the PLC 's memory before it can run. Nowadays, everyone has a computer; we can use programming software to create the ladder diagram, connect the computer to the PLC using a dedicated cable , and then write the program into the PLC .
4. Simulation Operation
After the program is loaded into the PLC, a simulation run must be performed first. This can be done by using connecting wires to simulate various states of the input terminals and observing whether the output signals meet the design requirements.
