Lattice Semiconductor's fourth product based on the Nexus platform, the CertusPro-NX, brings significant innovation to the existing FPGA market. Manufactured using a 28nm FD-SOI process, this series of FPGAs boasts low power consumption and small size advantages, primarily targeting the low-density device market. Compared to the previously released Certus-NX, the new product increases the number of logic cells from 17K to 96K. In 2020, the general-purpose FPGA market became more diversified, with market size growing by approximately 10%; the CertusPro-NX can be used to implement various functions, with applications including 5G cellular networks, artificial intelligence, and the Internet of Things. These markets are constantly evolving, and FPGAs offer a powerful flexibility that ASICs lack.
The new product series includes two models: the CPNX-50K with 52K logic cells and the CPNX-100K with 96K logic cells, which are also the first engineering samples. As shown in Figure 1, the latter model has a programmable I/O supporting LPDDR4 DRAM (a first for similar FPGAs). Lattice has also tripled the internal memory capacity, allowing the CertusPro-NX to reduce power consumption during memory-intensive operations.
Figure 1: CertusPro-NX block diagram. The new FPGA includes 7.3 Mb of on-chip memory, a DSP module with 156 18x18 multipliers, programmable logic, and eight flexible 10Gbps SERDES channels (configurable to connect to DisplayPort or CoaXPress).
In designing the CertusPro-NX series, Lattice employed a 28 nm FD-SOI process. Despite initial skepticism surrounding this choice, Lattice achieved excellent results in terms of power consumption and soft error rate, crucial for winning over customers in numerous application designs. In addition to programmable logic, the CertusPro-NX features a hard-core module that further reduces power consumption. It also includes a 10G Ethernet port and a four-channel PCIe Gen3 controller. Lattice paid particular attention to the bitstream configuration module, resulting in exceptionally fast device startup times, completing configuration in less than 30 milliseconds.
The CertusPro-NX represents a significant improvement over its predecessor, enabling customers to implement advanced features in their FPGA-based designs. Lattice has doubled the number of logic cells, expanded on-chip memory capacity, upgraded the PCIe controller, and enhanced programmable I/O interfaces. Compared to Intel's Cyclone V GT series and Xilinx's ArTIx-7 series, the new product achieves best-in-class performance in the industry.
Machine vision and edge AI
In addition to expanding the programmable logic architecture of CertusPro-NX, Lattice has enhanced the platform's AI capabilities. The new device utilizes 7.3 Mb of internal memory, allowing customers to load lightweight neural networks to recognize objects, listen for keywords, or detect anomalous behavior. However, hardware is only one aspect of the design. Lattice's sensAI software suite works with frameworks such as Caffe, TensorFlow, TensorFlow Lite, and Keras, and is supported by the Lattice AI Compiler. This proven suite of solutions provides numerous Lattice customers with power- and resource-efficient optimized AI applications. The software platform is compatible with several of the company's FPGAs (CertusPro-NX compatibility is planned for later this year).
Machine vision applications at the network edge not only require hardware implementation of neural networks, but also functionalities such as sensor compatibility, sensor aggregation, and image preprocessing. In this regard, Lattice provides CertusPro-NX customers with sufficient flexibility through programmable I/O and SERDES modules. For example, many high-definition image sensors use the SLVS-EC interface, which is lacking in many network edge AI accelerators.
Programmable SERDES also supports various standards for transmitting data from the network edge to the system interior, including CoaXPress and 10G Ethernet.
The CertusPro-NX boasts significantly more on-chip memory than its competitors. Since DRAM operations increase power consumption and reduce throughput, neural networks operate optimally with all weights stored on-chip, minimizing DRAM access. Therefore, customers desire larger on-chip memory. Lattice's new FPGA can store up to 1 million 8-bit weights—almost twice that of the Cyclone V GT or ArTIx-7. Because more weights can be stored internally, the CertusPro-NX can run larger AI models without accessing DRAM, thus reducing power consumption.
When Lattice FPGAs do need to access DRAM, they use programmable I/O modules that support LPDDR4 and DDR3 memory up to 1066 Mbps. The CertusPro-NX is the first in its class to support LPDDR4—a generation ahead of competitors offering only DDR3 and lower standards. However, on average, this newer technology increases chip and system power consumption. But because the CertusPro-NX has larger on-chip memory and an optimized memory controller, it achieves new levels of energy efficiency by using both on-chip and external memory, reducing power consumption and memory access time. Long-term availability is also a concern for many markets, including embedded vision, and LPDDR4 alleviates this concern.
Visibility is a key factor in building smart homes and even smart cities. Most end users prefer inconspicuous IoT sensor designs, and small-size microprocessors are at the heart of such designs. The CertusPro-NX, with an area of only 81 mm², boasts the smallest package among SERDES-enabled products, being 33% smaller than the Cyclone V GT and 84% smaller than the ArTIx-7. This small FPGA size further increases the available space in designs, allowing OEMs to add more functionality or shrink the design size.
Industrial Internet of Things
The latest generation of Industrial Internet of Things (IIoT) is characterized by large-scale automation, thanks to advancements in connectivity and data analytics. To automate tasks such as sorting and packaging, smart factories require thousands of IoT devices that generate and process terabytes of data daily. The chips driving these devices must be small, low-power, and highly reliable. Lattice has adopted these principles in its latest generation of FPGAs to help customers fully prepare for Industry 4.0.
Compared to competing CMOS-based FPGAs, the CertusPro-NX employs FD-SOI to reduce power consumption. One way to quantify this power advantage is to examine the power estimators from various vendors. Assuming a design requiring 65 K logic cells, utilizing 75% of the DSP and memory, and running two 5Gbps SERDES channels, the CertusPro-NX, operating at an 85°C junction temperature and 125MHz frequency, consumes 75% less power (dynamic + static) than the ArTIx-7 and 65% less power than the Cyclone V GT, as shown in Figure 2.
These data demonstrate the significant power consumption advantages of the FD-SOI process. This manufacturing technology uses an insulating layer on the substrate, reducing leakage current by up to 75% compared to other 28 nm Bulk CMOS products; and leakage current is a major factor contributing to static and standby power consumption.
As OEMs enhance product performance by increasing power consumption, Intel and Xilinx FPGAs will exceed their junction temperature thresholds faster than Lattice FPGAs. With its leading power efficiency, the CertusPro-NX offers more power and thermal headroom, helping OEMs reduce system size and lower thermal management costs. Furthermore, systems operating below junction temperature do not require fans prone to mechanical failure.
Heat dissipation is particularly critical for industrial motor control. Motors are often sealed to prevent dust particles from entering and shortening their lifespan. However, during operation, heat can accumulate in the motor and raise the ambient temperature around the FPGA. Compared to competing products, Lattice's low-power solution allows FPGAs to control motors with higher torque without overheating.
Figure 2: FPGA Power Consumption Comparison. LC = Logic Cell. Compared to similar FPGAs from Intel and Xilinx, Lattice FPGAs consume 65-75% less power. The power consumption estimates here are calculated for a 5 Gbps dual-channel SERDES application at 125MHz and a junction temperature of 85°C, with 75% resource utilization. (Source: Lattice)
FD-SOI also offers the added advantage of eliminating single-event upset (SEU) errors. These errors occur when radiated particles pass through a device and interact with memory or register cells, causing incorrect flips in the device's logic state and potentially corrupting memory or data paths. Compared to Artix-7, CertusPro-NX reduces the number of soft errors by 99% without requiring soft error detection logic and error correction code. This approach improves system reliability and simplifies customer design.
The CertusPro-NX has a mean time between failures (MTBF) 110 times that of the Artix-7. This feature meets the reliability requirements of automotive and medical systems; it also reduces maintenance costs by eliminating the need for frequent field adjustments and ensures the continuous operation of critical functions. The higher MTBF also improves the safety of industrial robots, as uncontrolled FPGAs entering unknown states can lead to machine malfunctions, resulting in personal injury or property damage.
OEMs typically need to pair FPGAs with other system components, requiring high-bandwidth inter-chip interfaces to prevent data flow bottlenecks. The new CertusPro-NX features a four-channel PCIe Gen3 controller that supports this type of connectivity. Its competitors typically only support PCIe Gen2, with each channel being 50% slower than PCIe Gen3. The higher SERDES bandwidth combined with the newer PCIe technology allows CertusPro-NX customers to overcome chip interconnect bottlenecks that might be difficult to achieve with other solutions.
5G applications
To better serve wireless networks, base station OEMs separate the control plane and user plane, allowing each plane to scale independently—a key feature of 5G networks, as these two planes change annually with each new specification released by 3GPP. The control plane is modular, allowing wireless network vendors to break its functionality down into multiple chips or integrate it onto a single chip. It handles various tasks, including authentication, client (UE) session management, and unified data management.
While a CPU can perform all these functions, it is less efficient than an FPGA. Industry estimates suggest that OEMs require highly efficient hardware because each 5G base station consumes 70% more power than a 4G base station. Given flexibility and power constraints, base station OEMs typically need FPGAs to assist in enhancing processors or ASICs. Lattice's new product consumes less power than the Artix-7 and Cyclone V GT, simplifying thermal management for base stations.
5G small base stations face limited space and high data throughput. CertusPro-NX boasts the smallest size among comparable chips with SERDES functionality, making it ideal for small-size designs where data rates are not limited. As shown in Figure 3, CertusPro-NX's leading 75 Gbps SERDES bandwidth is 36% higher than Artix-7 and more than twice that of Cyclone V GT. For high-bandwidth functions such as packet management, Lattice FPGAs offer significantly higher throughput and superior area efficiency thanks to their larger SERDES bandwidth.
Figure 3: Total SERDES Bandwidth. CertusPro-NX outperforms competitors by more than double, offering a significant advantage in data-intensive operations such as unified data management in 5G base stations. (Data Source: Lattice)
in conclusion
Lattice Semiconductor launched the CertusPro-NX primarily to meet the growing market demands of machine vision, industrial IoT, 5G cellular networks, and others. The device's optimized internal memory and LPDDR4 minimize power consumption for memory-intensive operations such as neural networks. FD-SOI technology reduces power consumption and failure rates, making next-generation devices more reliable and cost-effective. The new FPGA's 10Gbps SERDES and industry-leading package size make it ideal for small systems supporting data processing, such as 5G cellular networks. Beyond its excellence in these areas, OEMs can also apply it to many other sectors, including defense, automotive, and frame capture.
The three FPGAs described in the article contain roughly the same number of logic cells, but Lattice's product has a significant advantage due to its support for LPDDR4. In contrast, the other devices still use DDR3 memory. CertusPro-NX also offers larger internal memory and leading SERDES bandwidth. Customers can not only process and transmit more data using Lattice FPGAs, but also reduce power consumption by up to 75% and board area by 84%.
With the launch of CertusPro-NX, Lattice has injected new vitality into this important area that has received relatively little investment over the years. Its main competitors haven't released any new low-cost architecture products in the past decade, giving it the opportunity to solidify its market position with new technologies such as PCIe Gen3 and LPDDR4. This strategy allows Lattice to maintain its lead in power consumption and size for low-power FPGAs. Building on the innovative technologies of its predecessor, CertusPro-NX expands memory, SERDES, and logic functions to better serve emerging markets such as 5G base stations, industrial IoT, and machine vision.
Aakash Jani is a Senior Analyst and Editor-in-Chief of The Microprocessor Report at The Linley Group. The Linley Group provides clients with the most comprehensive analysis of microprocessors and SoC design. We analyze not only business strategies but also the technical aspects. Our featured articles cover topics including embedded processors, mobile processors, server processors, AI accelerators, IoT processors, processor IP cores, and Ethernet chips .
