Abstract: This paper introduces an embedded system for digital video compression and recording implemented using the ARM7 microcontroller LPC2214 and the MPEG-1 compression chip SZ1510. Under the control of the LPC2214, the SZ1510 completes real-time compression and stream synthesis of audio and video data, while the LPC2214 simultaneously handles stream transmission and storage control. The I/O ports of the LPC2214 are used to expand the IDE interface, allowing direct driving of large-capacity hard drives and CF memory cards. Keywords: ARM, MPEG-1, embedded system, digital video Introduction With the rapid development of computer technology, multimedia, and data communication technology, the application of digital video is becoming increasingly widespread, such as video surveillance, video conferencing, and mobile television. The massive amount of digital video data is unfavorable for transmission and storage, greatly limiting its application. The only way to solve the problem of video data storage and transmission is to compress the video data. Common video compression methods include the MPEG series and H.26x series. Considering the maturity, cost, and main applications of compression technologies, MPEG-1 is adopted as the compression standard, and an embedded digital video recording system based on an ARM processor is designed. This system is suitable for various applications such as video surveillance and video conferencing. It can also be installed on aircraft to record various information during flight and training in real time. Currently, there are many PCI bus-based MPEG-1 video compression cards and PC-based network video servers on the market. Compared with these, our designed video recording system has advantages such as low cost, small size, and low power consumption. 1 System Working Principle The design of the video compression and recording system focuses on the embedding of the controller and overall portability. This system mainly consists of three parts: a compression section, a control section, and a storage section. The structural composition of the video recording system is shown in Figure 1. The compression section consists of an MPEG1 audio and video compression circuit, whose main function is to decode, digitize, and compress the input audio and video signals, generating an MPEG1 program stream and transport stream. The control section consists of an ARM minimum system, used for controlling the entire system, managing data streams, and controlling the IDE interface. The storage section consists of a large-capacity hard drive or CF memory card, enabling real-time, long-term recording of compressed data. Upon system startup, the ARM processor initializes the entire compression system. First, it configures the internal registers of the SZ1510 via the HOST interface and initializes the SAA7113H video decoder using the SZ1510's serial interface to simulate an I2C bus. After setting the MPEG-1 compression format and data rate, the system begins normal operation. Audio and video signals undergo A/D conversion via the AK4550 audio processing chip and the SAA7113 video processing chip, outputting an 8-bit PCM format digital audio signal and a 4:2:0 YCbCr digital video signal. This signal is then fed into the SZ1510 audio and video compression and acquisition chip for processing, converting the digital audio and video data into a mixed video file conforming to the MPEG-1 format. Finally, the MPEG-1 data stream is written to the hard drive or CF card via the IDE interface under the control of the ARM processor. During operation, the ARM continuously monitors relevant signals and adds corresponding markers to the image until a power-off signal is received, at which point the system automatically terminates the compression process. 2 Hardware Circuit Design Since the MPEG-1 compression algorithm requires a large amount of computation, it is difficult to complete in real time using software. Therefore, this system mainly relies on a dedicated chip to achieve efficient compression of video signals. Currently, commonly used MPEG-1 compression chips include VW2010, W99200F, and WIS 7007SB. This design uses the Zapex SZ1510 MPEG-1 A/V encoding chip, which performs synchronous encoding of audio and video itself. Its 16-bit HOST interface makes it easy to connect to various microprocessors. In addition, this chip can also directly control the video decoding chip SAA7113H, the audio decoding chip AK4550VT, and the SDRAM (KM416S1020CT-G10). The CPU uses the Philips ARM7TDMIS core microcontroller LPC2214, which controls the data reading and storage of IDE interface hard drives or CF cards through its I/O ports. 2.1 MPEG-1 Compression Circuit Design The SZ1510 is an MPEG-1 and motion JPEG image encoder. Its built-in video compression core is optimized and suitable for efficient and real-time MPEG1 digital image compression. It has the characteristics of multiple functions, low power consumption and wide temperature range. At the same time, it integrates the high-performance DSP core of TI's TMS320C54X, which can encode audio and video synchronously according to the MPEG-1 standard. (1) Clock synchronization circuit setting SZ1510 is a complex video compression system. It needs to complete the synchronization of audio and video, the compression of MPEG-1 video and the composite and scheduling of internal data streams. The clock relationship is relatively complex, which is a difficult point in the system design. The clock configuration can be divided into the main clock, audio and video clock, video compression core clock, DSP core clock and extended I2S interface clock. Its functions and relationships are as follows: ◆ Main clock. The main clock of SZ1510 is a stable 27 MHz (CLK). This clock is multiplied to 81 MHz by PLL1 inside the chip to drive the video compression core and SDRAM of SZ1510. PLL2 is connected to the DSP core and is configured by software to work at 94.5 MHz for audio compression and system data stream composite. ◆ Audio and video clock. The video clock comes from the video decoder, with a typical value of 27 MHz. The audio clock is generated by dividing the video clock. ◆ I2S interface clock. In this system, the I2S interface slave mode is used in the audio and video synchronization design, and the serial clock and frame synchronization signal are generated by SZ1510. (2) Host port setting: SZ1510 is set as a slave device and is controlled by the host. Its HOST interface is the control and data exchange interface of SZ1510. SZ1510 can choose to multiplex or not multiplex the Intel and Motorola bus types; the non-multiplexed bus can be divided into 8-bit and 16-bit. The specific host port is configured by the HCONFIG[1:0] pin and the SysConfig[3] register. In this system design, HCONFIG0 is pulled low and HCONFIG1 is pulled high by the jumper, so that it works in the non-multiplexed 16-bit data bus mode of Intel 8051 type. 2.2 LPC2214 Microprocessor Circuit Design The LPC2214 is a 32-bit ARM7TDMI-S based CPU that supports real-time emulation and tracing. It features 16 KB of on-chip SRAM, 256 KB of embedded high-speed Flash memory, a 128-bit wide memory interface, and a unique acceleration architecture, enabling 32-bit code to run at a maximum clock rate of 60 MHz. The chip integrates multiple serial interfaces. The interface and control relationship between the LPC2214 and the SZ1510 is shown in Figure 2. In the design, it is important to maintain the synchronization of the SZ1510's read/write timing with its internal clock. Control word and data exchange is achieved by strobing the SZ1510 using CS3. 2.3 IDE Interface Design Since the LPC2214 chip does not have an IDE interface, general-purpose I/O ports are used in this system to simulate the read/write timing of ATA devices, enabling reliable read/write operations on the IDE hard drive. Figure 3 shows the connection diagram between the LPC2214 and the IDE hard drive. Among them, P2.16～P2.31 are used as data lines, P1.16～P1.20 are used as address and strobe signals, P0.17 and P0.20 are used as device reset and status request signals, and P0.21 and P0.19 are used for read and write control. 3 System Software Design The system software consists of a main program and several subroutines, and the workflow is shown in Figure 4. The main sub-modules are: SZ1510 setup and control, IDE interface driver, and file system management. 3.1 SZ1510 Setup and Control The SZ1510 has 128 registers, each with an index number. When the SZ1510 is working in non-multiplexed bus mode, external access to the registers is done through IOAR and IODR. During access, the index number of the register is first written to IOAR, and then the data to be written is written to IODR. The SZ1510 setup and control process is as follows: ① Write 0x40 to the interrupt enable register to enable the Ready interrupt; ② Wait for the SZ1510's Ready interrupt; ③ After the Ready interrupt, write 0x0A to the SZ1510's 0x1E register to set its internal DSP clock to 94.5 MHz; ④ Write 0x55 to the 0x013 register to perform a soft reset on the SZ1510; ⑤ Write 0x40 to the interrupt enable register 0x0C to enable the Ready interrupt; ⑥ Wait for the RDY interrupt; ⑦ After the Ready interrupt, initialize the SAA7113; ⑧ Perform a soft reset on the SZ1510, i.e., write 0x55 to the 0x0B register and 0x40 to the 0x0C register; ⑨ Wait for the Ready interrupt, and then load binary code into the SZ1510's internal DSP; ⑩ The binary code loading process for the SZ1510 internal video compression core is as follows: ◆ Write 0x04 to register 0x08 to send a start command; ◆ Wait for a Ready interrupt and clear the Ready interrupt; ◆ Write 256 bytes to register 0x01; ◆ Wait for an End of Data interrupt and then clear the interrupt; ◆ Check if the code in the program space has been loaded completely. If not, continue loading. 3.2 IDE Interface Driver This system uses the LPC2214's general-purpose programmable I/O port to simulate the read/write timing of an ATA device, enabling read and write operations to the hard drive. Here are the steps for simulating writing to an ATA device register (the steps for reading an ATA device register are similar): ① Disable system interrupts to prevent interrupts during register writing operations; ② Set the GPIO pin for simulating ATA interface data to output mode, preparing to output data to the device data line; ③ Set the corresponding address of the ATA device register; ④ Set the GPIO pin for simulating ATA interface data to the value to be written to the device; ⑤ Set the write ATA device register signal to low level; ⑥ Set the write ATA device register signal to high level; ⑦ Cancel the selection of the ATA device register address; ⑧ Set the GPIO pin for simulating ATA interface data bus to input mode, releasing the bus; ⑨ Enable system interrupts. 3.3 File System Management The small file system ZLG/FS [1] for embedded systems is used in this design, mainly for storing data in a standard file format and managing the entire file system. Meanwhile, to facilitate audio and video retrieval and querying, and to prevent the loss of large amounts of unsaved data due to unauthorized power outages, the system is configured to store compressed data in a new file named after the system time at regular intervals (30 minutes). 4. Conclusion Testing showed that the system can record external audio and video signals in real-time for extended periods, and the recorded compressed data stream conforms to the MPEG-1 international standard for image compression. In the design, the compressed video stream rate used is 1.5 Mbps, and the amount of video data for one hour is (1.5 Mbps/8) × 3600 = 675 MB. For a 40 GB hard drive, the system can continuously record for nearly 60 hours. The system is small in size and has low power consumption, making it suitable for real-time, long-term compressed recording of audio and video data in mobile environments.