Introduction to two topologies of multilevel high-voltage frequency converters
2026-04-06 08:20:01··#1
Abstract : Since its inception, the multi-level high-voltage inverter has demonstrated high value in energy saving and environmental protection, attracting numerous scholars to conduct research. This paper analyzes the two main topologies and principles of the multi-level high-voltage inverter. Keywords: Level 3; Series multi-level unit; Application 1 Introduction For high-voltage motors, if we use a traditional three-phase six-step inverter to control the motor, due to the excessively high voltage and the increased switching speed of power electronic devices, the output value of the switching devices will be very large. Since the neutral point of the motor winding is not grounded, there is a distributed capacitance between each winding of the motor and the ground. The change in output voltage is equivalent to the change in voltage across the capacitor, that is, the frequent charging and discharging of the capacitor. The charging and discharging will cause an impact on the insulation of the stator winding of the motor, and the larger the impact, the greater the impact. The voltage harmonics at the voltage output terminal can easily cause the motor to heat up and cause damage to the motor. In addition, due to the manufacturing reasons of the power electronic devices themselves, it is difficult to achieve the required 6KV or 10KV high voltage, so it is necessary to study the topology of the frequency converter. The multilevel converter first attracted the interest of researchers at the IEEE IAS Annual Meeting in 1980. A. Naba et al. from Nagaoka University of Technology in Japan proposed a three-level circuit structure with neutral point clamped (NPC) [1]. The basic idea is to obtain a multi-level stepped waveform output through a certain main circuit topology to be equivalent to a sine wave. Since the multilevel converter has high requirements for power inverter devices and control circuits, it did not receive much attention at first. Until the 1990s, with the mature application of GTO and IGBT and the emergence of new fully controlled devices such as IGCT and IEGT, as well as the popularization of high-performance digital control technology with DSP as the core, the research and application of multilevel converters have developed rapidly. At present, a variety of multilevel circuit structures have been proposed. According to the voltage clamping method of the main switching device, they can be divided into three categories: diode clamped (also known as neutral point clamped NPC), capacitor clamped and cascaded multicell [2]. 2 Three-level frequency converter and its derived schemes 2.1 Working principle of three-level frequency converter Figure 1 Three-level circuit principle structure diagram Figure 1 shows the structure diagram of the single-phase inverter part of the three-level inverter. In the figure, S1 to S4 are the inverter devices. The inverter devices can be GTO, IGBT or IGCT tubes. V1-V4 are freewheeling diodes for the inverter, while V5 and V6 are clamping diodes. For a balanced circuit, all diodes must be selected with the same power rating and voltage withstand capability. Capacitor Ed filters out harmonics from the rectified voltage, resulting in a relatively stable DC voltage. Point C is the center point, serving as the reference voltage for the base point. By controlling the on/off state of power inverters S1-S4, three different voltage levels can be output: +Ed when S1 and S2 are on, 0 when S2 and S3 are on, and -Ed when S3 and S4 are on. As shown in the schematic, three different voltages can be output at the output terminal; therefore, this type of inverter is called a three-level inverter. Controlling the on-time of S1-S4 allows for the output of an approximately sinusoidal adjustable voltage to drive the motor, i.e., SPWM modulation inverter mode. We can establish the operating state table as shown in Table 1. Table 1 shows the operating states of each switch. Based on the above principles, we can construct a three-phase three-level voltage-type frequency converter using 12 fully controlled inverter devices and clamping diodes. Figure 2 below shows the principle structure diagram of the three-phase three-level frequency converter, which is also called a center-point clamping frequency converter because it has a common base point. According to the switching operating states of the single-phase inverter devices, the inverter has three stable operating states: P, O, and N. Now we will study the output voltage filtering by controlling the switching operating states of the inverter devices using single-pulse delay α-angle triggering. If the frequency converter supplies power to a three-phase Y-connected resistive load, Figure 3 shows the voltage form of the single-phase output, and Figure 4 shows the load connection diagram. Figure 2. Schematic diagram of a three-level voltage inverter. Figure 3. Waveform of single-phase output voltage under single-pulse control. Figure 4. Y-connection diagram of resistive load. If we assume the midpoint of the load is O' and the center point of the power inverter clamp is O, then the phase voltage U[sub]AO'[/sub] of the load can be expressed by the following formula: The formula represents the potential difference between O' and the clamp midpoint O. To ensure the triggering and conduction of the inverter devices, we set the triggering delay angle to: , i.e. The triggering control angles of phases A, B, and C differ by 120°, i.e. Then we can know the output voltage of each of the three phase ports. Table 2.5 shows their output voltages at different times. Table 2 shows the voltage of each phase of the three-phase three-level output terminal within one cycle. According to Table 2 and Equation (1), the voltage range of phase A within one cycle is listed as follows: The above calculations are the output voltages of phase A in each time region within the first half of the cycle. The absolute values of the output voltages in the second half of the cycle are equal, but the directions of the voltages are exactly opposite, namely 0, -2/3E[sub]d[/sub], -E[sub]d[/sub], 4/3E[sub]d[/sub], -E[sub]d[/sub], -2/3E[sub]d[/sub], and among the three-phase outputs, phases B and C lag phase A by 2TT/3 and 4TT/3, respectively. The output voltage of phase B also changes every π/3. Based on the above calculations of U[sub]AO'[/sub] and U[sub]BO'[/sub], the line voltage U[sub]AB[/sub] between the two phases at the output terminal can be obtained, as shown in Table 3. Table 3 Output voltage table of line voltage According to Table 3, we can draw the voltage output waveform diagram between phases A and B: Figure 5 Waveform of three-phase three-level output line voltage From the waveform diagram 5, we can see that the output line voltage waveform is similar to a sine wave, but before connecting to the motor, it is necessary to filter it with a reactor and a capacitor to meet the control requirements of the motor input voltage. Since the voltage harmonics at the direct output terminal are relatively large, the three-level frequency converter must have a reasonable filtering circuit before it can control the motor for frequency conversion. Through the control of single pulse, we can see that if the three-level frequency conversion mode is controlled by SPWM, the output voltage waveform will be closer to a sine wave. Of course, its filtering is still very large, and it must be connected to a large reactor or capacitor to reduce harmonics before the motor is controlled for frequency conversion speed regulation to avoid the influence of harmonics and damage to the motor. 2.2 Derivative schemes of three-level frequency conversion (1) Diode clamping type multilevel At the IAS annual meeting in 1983, A. Bhagwat et al. further extended the three-level to arbitrary multilevel structure. [3] As shown in Figure 6, a five-level inverter with diode clamping structure is used. Its principle is similar to that of a three-level inverter, except that the output voltage has more steps and better waveform. Under the same device withstand voltage, it can output a higher AC voltage, which is suitable for making inverters with higher voltage levels. However, the number of devices and the complexity of the system are also greatly increased. Figure 6 Inverter two-phase circuit of diode clamping five-level inverter The switching state and output voltage of diode clamping five-level inverter are shown in the following table: Table 4 Switching state and output voltage of diode clamping five-level inverter Through analysis, it can be seen that the main characteristics of diode clamping type multilevel circuit are: ① Multiple diodes are used to clamp the corresponding fully controlled devices to solve the problem of device voltage equalization. Each phase bridge arm of the M-level circuit requires 2 (M-1) fully controlled devices. A large number of clamping diodes are required, which makes the NPC circuit above seven levels lose its practical value. ② The DC side uses capacitor voltage division to form multi-level levels, which does not require a complex tortuous connection transformer. M-level circuits require M-1 voltage divider capacitors, and the problem of capacitor voltage imbalance needs to be solved in the control. ③ The operating frequency of the switching transistors of each phase bridge arm is different, and the conduction time of the middle switching transistor is much longer than that of the outer switching transistor, resulting in a heavier load. This can easily cause the middle switching device to burn out. The control of the switching device is complicated, making it difficult to control the seven-level and above in practical applications. (2) Capacitor clamping type multilevel capacitor clamping flying capacitor type (Flying Capacitors) multilevel circuit was proposed by TAMeynard et al. at the PESC annual meeting in 1992 [4]. The capacitor clamping type five-level circuit is shown in Figure 7. The main features of the flying capacitor type multilevel circuit are: ① It uses series capacitors connected between the switching devices for clamping. Each phase bridge arm of the M-level circuit requires (M-1)(M-2)/2 clamping capacitors, and the DC side voltage divider capacitor is the same as that of the diode clamping type circuit. ② The selection of the switching state is more flexible than that of the diode clamping type circuit, which is conducive to balancing the conduction time of the switching device and the capacitor voltage. ③ Due to the large size, high cost and short service life of DC filter capacitors, their practical value is not as good as that of diode clamping circuits. In recent years, several improved circuits based on the above two structures have been proposed. Among them, the most representative is the unified topology of clamping multilevel circuit proposed by FZ Peng et al. at the IEEE IAS2000 conference [5]. Figure 8 is its single-phase circuit diagram. Both diode clamping and capacitor clamping circuits can be derived from this circuit topology, and the circuit can achieve automatic balancing of DC capacitor voltage. 2.3 Unit series multilevel high voltage inverter In order to increase the number of levels to improve the output voltage level and further reduce the high-order harmonic content, M. Marchesoni et al. proposed the H-bridge cascaded multilevel inverter circuit at the PESC conference in 1988. Figure 9 is the circuit diagram of unit series seven levels. Figure 7. Two-phase inverter circuit of capacitor-clamped five-level inverter. Figure 8. Single-phase inverter circuit diagram of clamped multi-level circuit with unified topology. Figure 9. Three-phase unit cascaded seven-level circuit diagram. The unit cascaded multi-level inverter uses several low-voltage power units connected in series to achieve high-voltage output. This circuit structure and method can easily be expanded to more levels to achieve higher voltage output. The main characteristics of unit cascaded multi-level are: ① Each phase is composed of N H units cascaded together, and the number of output phase voltage levels of the inverter circuit is M=2N+1. Since each power unit has the same structure, it is easy to modularize and package. When a unit fails, it can be bypassed, while the remaining power units can continue to operate, improving the reliability of the system. ② The DC side is powered by an independent power supply, which does not require clamping devices and eliminates voltage balancing problems. If the DC power is supplied by a three-phase uncontrolled rectifier circuit, the rectifier side needs to be connected to a transformer with multiple windings (phase-shifting transformer), which increases the size of the device. However, the use of multiple rectification reduces the input current harmonics. ③ By controlling each power unit according to a specific rule, the waveforms of each power unit can be superimposed to obtain a multi-level output. This control method is simpler than the overall control of each bridge arm by a clamping circuit and is easier to expand to higher voltage output. Although cascaded multi-level high-voltage inverters require a large amount of isolated DC power, the cascaded structure still has high performance and is widely used in practical industrial applications. Since the early 1990s, multi-level inverters have been increasingly widely used in high-voltage, high-power applications, especially in reducing grid harmonics and compensating for grid reactive power. Multi-level inverters can not only reduce the voltage rating of switching devices, but also greatly improve the output waveform of the inverter and reduce the harmonic distortion rate of the output voltage. 3 Applications of Multi-level Inverters After years of research, the main circuit topology of multi-level inverters is theoretically complete. Among various topologies, the diode-clamped three-level inverter and the cascaded inverter with equal voltage units have been put into practical use. Representative products of diode-clamped three-level inverters include ABB's ACSI00 series high-voltage inverters and GE's INNOVATION series high-voltage inverters. Both are based on IGCT three-level circuits, but their maximum voltage application is limited to 4kV, and they still exhibit significant high-order harmonic content. A representative product of cascaded inverters is the perfect harmonic-free high-voltage inverter from Robicon, Inc. Beijing Leadway's Harsvert-A series high-voltage inverters use IGBTs as power switching devices and can be applied to voltage levels up to 10kV. They have also found practical applications in reactive power compensation in power systems. In 2000, ALSTOM developed the world's first ±75Mvar STATCOM based on a cascaded structure to improve power transmission from northern to southern England. Tsinghua University and Shanghai Electric Power Company in my country are collaborating on a ±50Mvar STATCOM based on an IGCT cascaded structure. Research on multilevel inverters in high-power power supplies and high-power active power filters has also begun. 4. Summary This paper analyzes the structure of several commonly used topologies in existing high-voltage inverters and points out the characteristics of these main circuit topologies in application. Multilevel high-voltage frequency converters have the advantages of high speed regulation accuracy, high power factor, perfect harmonic elimination, and significant energy-saving effect, making them worthy of widespread application. References: [1] Li Yongdong, Yi Peng. Review of the development of high power high performance inverter technology [J], Electric Drive, 2000, (6): 3-9 [2] Qi Yue, Yang Geng, Dou Rixuan. Topology analysis based on multi-level conversion inverter circuit, Journal of Electrical Machines and Control, 2002, 6 (1): 74-79 [3] Shan Qingxiao, Li Yongdong, Pan Mengchun. New progress in cascaded inverters. Journal of Electrical Engineering, 2004 (2): 1-9 [4] Wu Hongxiang, He Xiangning. Simulation study on PWM control method of cascaded multi-level converter, Proceedings of the Chinese Society for Electrical Engineering, 2001, 21 (4): 42.4 [5] Ding Kai, Zou Yunping, Zhang Xian, et al. Research on cascaded multi-level inverter, Power Electronics Technology, 2002, 36 (2): 26-28