Introduction With the development of CMOS (Complementary Metal-Oxide-Semiconductor) technology and increasing market demand, CMOS image sensors have developed rapidly. Due to the use of CMOS technology, pixel arrays and peripheral support circuitry (such as the image sensor core, a single clock, all timing logic, programmable functions, and A/D converters) can be integrated onto a single chip. Compared to CCD (Capacitively Coupled Device) image sensors, CMOS image sensors integrate the entire image system onto a single chip, offering advantages such as small size, light weight, low power consumption, easy programming, and ease of control. Therefore, the application of CMOS image sensors has become increasingly widespread. However, most image acquisition systems based on CMOS image sensors currently on the market use a DSP connected to the image sensor. The DSP controls the image sensor, acquires the image, and then transmits the image data to a PC via a USB interface for further processing. Such image acquisition systems are costly, consume a lot of power, and have certain size limitations, making them unsuitable for some simple applications. This paper designs a CMOS image sensor data acquisition system based on the S3C2410. This system is more cost-effective, has a simpler structure, and a more novel design. 1. CMOS Image Sensor Structure, Performance, and Working Principle This system uses the OmniVision OV7141 monochrome CMOS digital image sensor. The OV7620 is a single-chip VGA mode monochrome digital camera chip with 640×480=307,200 pixels and can output digital image data at a maximum speed of 30 frames per second. It features high sensitivity, wide dynamic range, anti-blooming, and zero halo characteristics. All image characteristic parameters, such as exposure, gain, white balance, frame rate, output image data format, image timing signal polarity, window size and position, can be set through the SCCB interface and take effect immediately. The main characteristics of the OV7141 are as follows: image size 3.6 mm × 2.7 mm; pixel size 5.6 μm × 5.6 μm; pixel count 640 × 480 pixels (VGA), 320 × 240 pixels (QVGA); signal-to-noise ratio > 46 dB; minimum illumination 3.0 V/(Lux·s); dark current 30 mV/s; dynamic range 62 dB; power supply DC 3.3 V and DC 2.5 V; power consumption 40 mW (operating), 30 μA (sleep). The design of the CMOS image array is primarily based on a progressive scan field readout system and an electronic shutter with synchronized pixel readout circuitry. The electronic exposure control algorithm (or system rules) is based on the overall image brightness. When the scene (or setting) is normal, the exposure is generally ideal. However, when the scene lighting is unsuitable, the white/black ratio should be adjusted using AEC (automatic exposure control) to meet application requirements. The image acquisition window can be arbitrarily set, and the data output mode can be selected as progressive or interlaced working mode. The OV7141 internally embeds an 8-bit A/D converter, thus enabling synchronous output of an 8-bit digital video stream D[7…0]. Simultaneously with the digital video stream output, it also provides a pixel synchronization clock PCLK, a horizontal reference signal HREF, and a frame synchronization signal VSYNC to facilitate image reading by external circuits. The timing relationship between pixel data output and PCLK, HREF, and VSYNC is shown in Figures 1 and 2. 2. Introduction to S3C2410 Samsung's 16/32-bit RISC processor S3C2410 provides a low-cost, low-power, high-performance small microcontroller solution for handheld devices and general-purpose applications. To reduce overall system cost, the S3C2410 offers the following rich internal components: separate instruction and data caches, an integrated MMU, LCD controller (supporting STN & TFT), NAND Flash system boot support, system manager (chip select logic and SDRAM controller), 3-channel UART, 4-channel DMA (Direct Memory Access), 4-channel PWM (Pulse Width Modulation) timer, I/O ports, RTC, 8-channel 10-bit A/D converter and touchscreen interface, IIC-BUS interface, USB host, USB device, SD master card and MMC card interface, 2-channel SPI, and an internal PLL (Phase Locked Loop) clock multiplier. 3. CMOS Image Sensor and Controller Interface Circuit Design The interface circuit design should primarily consider the data output circuit interface, control circuit interface, and IIC bus interface of the S3C2410 CMOS image sensor and controller. 3.1 Data Interface Module Since each imaging unit of a CMOS image sensor is individually addressed like a memory cell in DRAM, and the OV7141 has an embedded 8-bit A/D converter, it can synchronously output an 8-bit digital video stream D[7…0]. Therefore, connecting it to the data line is the same as with DRAM; simply connect the data line directly to the S3C2410's data bus. The wiring connection is shown in Figure 3. However, CMOS image sensors also differ from memory: memory in a computer system is always treated as a slave device, only opening its data bus when the controller performs read/write operations on it, otherwise remaining in a closed state (high impedance state); while the OV7141 image sensor, once it starts acquiring image data, completely disregards whether the main controller in the system performs read/write operations on it, always outputting data to its data bus according to its own timing, which may cause data bus conflicts. To avoid this bus conflict problem, a tri-state bus driver needs to be connected between the system controller's data bus and the OV7141 image sensor's data bus. The enable pin /OE of this driver is selected by the S3C2410's memory cell chip select signal nGCS1. This allows the S3C2410 controller to read and write to the image sensor as if it were reading and writing to memory. 3.2 Control Interface Module When the CMOS image sensor operates in progressive scan mode, it outputs one frame of data after outputting a frame synchronization signal. A line synchronization signal is also output before each line of data. Each valid pixel signal triggers a signal output at one point. The output valid window is determined by the HREF signal. As shown in Figures 1 and 2, the frame synchronization signal VSYNC marks the beginning of a frame of data. Then, under the action of each PCLK signal, the sensor sequentially outputs each pixel's data from left to right. When the output pixel data is valid data, HREF is at an active level. After all the data in a frame has been output, another frame synchronization signal VSYNC is generated, and the transmission of the next frame of data begins. Based on the specific timing diagram above, DMA can be used to transfer data from the image sensor to the DRAM. The frame synchronization signal VSYNC can be used as an interrupt input signal for the main controller to initialize the DMA controller. The horizontal synchronization signal HREF can be used as an external interrupt input signal to count the output of each line of data. The output data synchronization signal PCLK can be used as a DMA transfer request signal to request the transfer of one pixel's data information. The connection circuit is shown in Figure 4. 3.3 IIC Bus Interface Module CMOS image sensors currently commonly use a subset of the IIC bus functionality, therefore this interface is simpler than a complete main IIC bus. Hardware connection only requires connecting the SIO_C and SIO_D pins of the OV7141 to the SCL and SDA pins of the S3C2410, respectively, as shown in Figure 4. The IIC bus consists of a bidirectional data line SDA and a clock line SCL. Users use open-collector gates for wired-AND bus connection. The IIC bus communication protocol is shown in Figure 5, including start signal, end signal, acknowledge signal, and data valid status. When SCL remains high, SDA transitions from "1" to "0", indicating a start signal; when SCL remains high, SDA transitions from "0" to "1", indicating a stop signal. During data transmission, SDA is valid when the clock is high and replaces data when it is low. Both start and stop signals are generated by the master IIC. Data transmitted via SDA is in bytes (8 bits), with the most significant bit first and the least significant bit last. A low-level acknowledgment signal is sent after each byte by the receiving end. The read/write cycle is as follows: When performing an IIC bus write operation, the CMOS sensor-specific ID write address is sent first, followed by the address of the register to be written (sub_address), and then the data. When performing an IIC bus read operation, the CMOS sensor-specific ID write address is sent first, followed by the address of the register to be written (sub_address), then the CMOS sensor-specific ID read address, and finally the data is received. Different CMOS sensors have different ID addresses. For the OV7141, it is 42H (write) and 43H (read). 4. Software Driver Design for CMOS Image Sensors CMOS image sensors require a driver from the S3C2410 controller to function properly and output correct image data. To achieve fast data transfer between the CMOS sensor and main memory (DRAM), DMA (Direct Memory Access) can be used. DMA is a fast data transfer mechanism that automatically exchanges data in batches between peripherals and main memory without CPU intervention. Since the processing unit uses the S3C2410, DMA, interrupts, and the IIC bus interface are all integrated within the controller. Therefore, the entire software driver only needs to configure two functional modules: the S3C2410 main controller and the OV7141 via the SCCB port. 4.1 Settings for the S3C2410 main controller: a) Set the DMA source address to the address of the control bus driver; this address value remains unchanged for each transfer. b) Set the DMA target address to the starting address of the memory region where image data is to be stored; this value increments by 1 for each transfer. c) Set the DMA counter to the number of pixels in the effective window. d) Set the DMA interrupt to software trigger and set PCLK, VSYNC, and HREF as external interrupt trigger signals to control the output of image data. 4.2 Setting the OV7141 via the SCCB interface: a) Read the OV7141's IC and ID registers to determine if the chip is functioning correctly; b) Set register 13 to 0x07 to enable AGC and white balance; c) Set register 14 to 0x00 to set the effective window to 640×480 pixels (VGA); d) Set registers 17, 18, 19, and 1A to set the start and stop of the HREF and VSYNC signals; e) Set register 28 to 0x60 to set both black-and-white mode and progressive scan mode. 5. Experiments and Discussion In this system, the image sensor's clock is supplied by an external 24 MHz crystal oscillator. The main controller S3C2410 operates at 200 MHz. The CMOS image sensor OV7141 operates in progressive scan mode, with an image acquisition window of 640×480 pixels. Data is stored in a single SDRAM chip within the system. Experiments show that the system can stably acquire 15 frames of image data per second. To increase the image acquisition rate, a dual-port SDRAM can be added as a data output buffer, which improves the rate, but dual-port SDRAM is expensive. Alternatively, using a main controller that can operate at a higher frequency can also increase the acquisition rate. This design is an embedded image acquisition system based on a 32-bit processor. The main controller S3C2410 is directly connected to the image sensor, along with some memory chips, forming a simple image acquisition system. Compared to most PC-based image acquisition systems, it has advantages such as simple structure, low cost, small size, low power consumption, and good versatility, making it particularly suitable for applications with high requirements for size, cost, and power consumption, such as fingerprint recognition systems currently on the market. Therefore, this system has broad application value and certain research significance.