Abstract: To improve the anti-interference performance of centralized smart meters, a combination of hardware and software measures were adopted in the design. Hardware-wise, the MAX691A power monitoring and watchdog circuit were mainly selected; software-wise, data verification, backup, insertion of no-operation, and software traps were mainly employed. Practical testing has shown that the system has excellent security and reliability. Keywords: Smart meter, microcontroller, anti-interference Introduction Currently, the vast majority of urban and rural residents in China still use manual methods for electricity meter reading. This outdated method consumes a large amount of manpower and resources, and the data collection time span is large, resulting in low accuracy. Therefore, relevant national departments have stipulated that automatic meter reading systems will gradually replace manual meter reading. However, this means that traditional mechanical meters cannot meet the performance requirements. Therefore, we adopted microcontroller automatic measurement and control technology to design a centralized smart meter that can be used independently or in conjunction with automatic meter reading systems. To ensure its long-term stable, safe, and reliable operation, a comprehensive system anti-interference design is necessary. The following is an introduction to the relevant content: The necessity of system anti-interference design Since centralized smart meters operate in residential areas, they are easily subject to various electrical and electromagnetic interferences from within and outside the system, with power supply system interference being the main one. Among household appliances, many are inductive loads, and their rapid switching can cause noise interference to the power grid, which may lead to data corruption or crashes of the microcontroller. The rules are as follows: (1) When the amplitude of the interference pulse is small, it has little effect on the microcontroller; (2) When the amplitude of the interference pulse is large, it causes the microcontroller to reset; (3) When the amplitude of the interference pulse is large and there are many pulses at an instant, it may cause data corruption or crashes of the microcontroller. Smart meters are required to be connected to the grid continuously for many years. Any abnormal phenomena that occur during operation (data corruption, crashes, etc.) must be able to be safely recovered. Therefore, the requirements for anti-interference are very high. If effective anti-interference measures are not taken, when the system encounters strong interference signals during operation, its performance reliability and operational safety will be reduced, which will cause significant economic losses to users, property management or power departments, and may even lead to economic disputes. The basic principles of anti-interference design are: suppressing interference sources, cutting off interference propagation paths, and improving the anti-interference performance of sensitive devices. Therefore, to ensure the safe and reliable operation of this smart meter system, a crucial aspect is the anti-interference design of the microcontroller system, which mainly includes hardware and software anti-interference. System Anti-interference Design 1. Hardware Anti-interference Design The power signal acquisition and output section uses optocouplers. The primary and secondary sides of the optocoupler are electrically insulated, thus providing strong suppression of ground potential difference interference and electromagnetic interference. While providing power to the system, the power supply also directly adds interference noise to the control circuit from the power supply end. The microcontroller's reset line, interrupt line, and other control lines are most susceptible to this external noise interference, so certain measures must be taken to suppress and eliminate this interference. Specific methods include adding shielding covers, isolation transformers, magnetic rings, and π-type filter circuits, but these can only reduce the number and amplitude of interference pulses, not fundamentally solve the problem. Therefore, it is also necessary to use a dedicated power monitoring chip for the microcontroller to improve the anti-interference capability of sensitive devices. A prominent feature of this system in terms of hardware anti-interference is the use of the MAX691A microcontroller system monitoring chip, and the design of the CPU security monitoring circuit. The MAX691A has the following functions: reset, data memory write protection, backup battery switching, watchdog timer and power monitor. The connection circuit is shown in Figure 1. MAX691A main pins and their functions: (1) VBATT: Backup power input terminal, can be connected to a 3.6V lithium battery or charging circuit. If not used, it should be connected to GND. (2) VOUT: Power output terminal. When VCC is higher than the upper limit of the reset voltage, VOUT = VCC; when VCC is lower than the upper limit of the reset voltage, VOUT is connected to VBATT. A 0.1μF capacitor needs to be added between VOUT and GND. (3) VCC: Working power input terminal, connected to +5V. (4) GND: Power ground terminal, is the reference point for all signals. (5) PFI: Power supply voltage comparator input terminal. When the voltage input at this terminal is lower than 1.25V, PFO (————) will go low. (6) PFO (————): Power-down output terminal, active low. In Figure 1, it triggers INT (————) 0 interrupt, and the interrupt service routine will perform emergency processing before the system power-down. (7) WDI: Watchdog feed terminal. When it holds a high or low level for 1.6 s (typical value), the internal watchdog timer overflows and triggers WDO (——————) signal output. (8) CE (————) OUT: Chip select signal output terminal. CE (————) OUT will only output a low level when CE (————) IN is low and VCC is normal, which can effectively prevent erroneous operation of the data storage. (9) CE (————) IN: Chip select signal input terminal. (10) WDO (——————): Watchdog output terminal, active low. If WDI is floating, WDO (——————) will remain high. (11) RESET (——————————): Low-level active reset terminal. When VCC is lower than 4.65V, RESET (——————————) becomes low. The typical value of the reset signal is 200ms. (12) RESET: High-level active reset terminal, open collector output. In addition, MAX691A also has functions such as oscillation frequency selection (pins 7 and 8), which can adjust the reset and watchdog timer time. In Figure 1, a differentiator circuit and an inverter are added so that WDO (——————) directly triggers the system reset, which greatly simplifies the anti-interference design of the software. 2. Software anti-interference design The software anti-interference measures adopted by this system are as follows: (1) Level detection is used for the input signal instead of edge detection to reduce the influence of various random interference pulses. (2) Important status register units are backed up. When the system status is damaged by interference, the information of the backup register unit can be queried in time to correct the status. (3) Before storing the power data, it is verified to ensure the correctness of the data. (4) The power data is stored in multiple addresses in both 6264 and 2465, and is backed up to each other to ensure that nothing goes wrong. (5) Set up a self-test program and set status flags in certain memory units. After the system is powered on, it will monitor them to ensure the high reliability of information storage, transmission and operation. (6) Insert no-operation instructions: Insert no-operation instructions before comparison condition jump instructions, absolute jump instructions, interrupt and stack instructions, and after data tables to improve the stability of the system. (7) When the program runs abnormally, such as the program "runs away", or the data in the data area and working register is corrupted, the following measures are taken: (a) Set up a monitoring and tracking timer. Since the system is designed with a CPU safety monitoring circuit, the program can be monitored by using the timer interrupt of MAX691A, i.e., the watchdog. As long as the program runs normally, the timer will not interrupt. When the program runs abnormally and cannot refresh WDI in time due to "running away" or other reasons, the watchdog timer will cause a crash reset. (b) A software trap is set in the program memory, filling the blank space with no-operation instructions and long jump instructions (LJMP ERR) to intercept the runaway program. Finally, a software forced reset is performed to return the program to its initial state. During the software reset process of the MCS-51 microcontroller, the interrupt return instruction RETI must be executed twice consecutively to ensure that the interrupt flag is cleared and the system returns to normal. The error handling procedure is as follows: ERR: CLR EA; Correct software reset entry, disable interrupts MOV 66H,#0AAH; Rebuild power-on flag MOV 67H,#55H MOV DPTR,#ERR1; Prepare for the first return address PUSH DPL PUSH DPH RETI; Clear high-level interrupt activation flag ERR1: CLR A PUSH ACC PUSH ACC RETI; Clear low-level interrupt activation flag Conclusion This centralized smart meter system has undergone comprehensive and effective system software and hardware anti-interference design, especially making full use of the powerful monitoring function of the MAX691A chip, realizing the system's three-state (power-on, power-off, crash) reset, data memory write protection, backup battery switching, watchdog timer, and power monitoring functions. This greatly improves the system's anti-interference capability, ensures the safety and reliability of system operation, and provides reliable technical support for the practical application and promotion of this smart meter.