1. Introduction Frequency synthesis technology has evolved through three generations: direct frequency synthesis, phase-locked loop (PLL) frequency synthesis, and direct digital frequency synthesis. Direct digital frequency synthesis (DDFS or DDS) is the hallmark of this third generation. Its main characteristic is computer involvement in frequency synthesis, which can be implemented in software, hardware, or a combination of both. The greatest advantage of a direct digital frequency synthesizer is its extremely fast frequency switching speed (down to a few microseconds), with controllable frequency, phase, and amplitude. The output frequency stability reaches the level of the system clock's stability, making it easy to integrate. More importantly, because of computer involvement, the software's role can be fully utilized. Although existing dedicated DDFS chips offer many functions, their control methods are fixed and may not meet our needs. This paper designs a direct digital frequency synthesizer using an 80C51 microcontroller, a D/A converter, and some peripheral registers. The circuit design is simple, the frequency control is flexible, and it has good practicality, with signal accuracy errors within acceptable limits. 2. Basic Principles of DDFS First, the phase of a unit amplitude sine function is divided into the smallest possible equal intervals within the range of 0 to 2π radians. If represented by A bits of binary data, and divided into 2A intervals, the minimum phase interval should be: Calculate the unit sine function value for the corresponding phase point and represent it using D bits of binary data. Write this value into a ROM with A address lines and D data lines, forming a so-called sine table. The process of synthesizing the frequency involves controlling the change in phase increment (i.e., the number of minimum phase intervals θmin that the phase skips). Because the phase increment is different, the sampling points within a sine cycle are different. Sampling is performed under the control of the system clock, meaning the sampling period is constant. Thus, the period of the quantized sine wave formed by reading the corresponding function value from the ROM based on the accumulated phase increment and the corresponding point (representing the phase value) also changes with the phase increment, thereby achieving the purpose of synthesizing the desired frequency. The phase accumulator accumulates once per clock cycle based on the frequency code k in the frequency code latch. Its output (N bits) is returned to the other input of the adder as the augend for the next accumulation, and (A bits) is used as the address code for the ROM to address the corresponding sine function value (binary code). After being stabilized by the data buffer, this value is sent to the D/A converter to obtain a sine function value with an amplitude corresponding to the phase point of the PA output. At the next clock cycle, the accumulator increments by another k value, and the ROM again reads the sine value corresponding to the A-bit address code of the accumulator output, which is then sent to the D/A converter. This process continues, resulting in a stepped output value for the phase accumulator. Correspondingly, the D/A converter output is a stepped wave with a sine wave envelope. The overflow of the phase accumulator corresponds to the end of one cycle of the stepped sine wave, and the start of the next cycle. After smoothing by a low-pass filter, a sine wave with frequency f0 is obtained. Since the clock period Tc = (1/fc) is a constant and highly stable value, the output frequency is also very stable. 3. Specific Implementation of Main Functional Modules of the System 3.1 Frequency Code Latch (FR) and Phase Accumulator (PA) The frequency code latch consists of two 8-bit D-type latches 74LS373. Only D0 to D3 of the second latch are used, forming a 12-bit frequency code. The phase accumulator consists of three 4-bit full adders 74LS283, forming a 12-bit adder. The output of the adder passes through two 74LS273 registers. On one hand, the 12-bit output is fed back to the input of the full adder as the addend. On the other hand, the 10-bit output (discarding the lower 2 bits) is used as the address code for ROM addressing. The frequency code k output by the frequency code latch is used as the addend. Here, the 74LS273 register mainly acts as a data buffer. Both registers operate on the rising edge of the clock. 3.2 ROM Sine Table The ROM sine table is implemented using the internal program memory of the 80C51 microcontroller. Since the address A output by the phase accumulator is 10 bits, and each sine function value is represented by an 8-bit binary number, the capacity of the sine table is 1 kB. The 80C51's on-chip program memory capacity is 4 kB, which is sufficient, so there is no need to expand the external program memory. Using P3.1, P3.0, and P1.7~P1.0 of the 80C51 as 10-bit address inputs, a lookup table program reads the corresponding function value according to the address, and then outputs it through port P0 to the D/A converter. The lookup table method involves pre-calculating a table representing the relationship between variables and function values ​​that meets certain precision requirements, and then storing this table in the microcontroller's program memory. In this case, the independent variable is the cell address, and the corresponding function value is the content of that address cell. In microcomputer application systems, the tables generally used are linear lists, which are a commonly used data structure. A linear list is a set of n data elements a1, a2, ..., an, where each element has a linear positional relationship. Each time a table lookup occurs, the 10-bit address input from P3.1, P3.0, and P1.7 to P1.0 is first stored in two memory locations, 20H and 21H (the high byte is in 20H). This will serve as the address offset during the table lookup (the actual address of the function value stored in program memory = table start address + offset). 3.3 Digital-to-Analog Converter (D/A) The DAC0832 digital-to-analog converter has an 8-bit input digital value and a reference voltage Vref operating range of -10 to +10 V. It connects an external high-precision voltage source to an internal resistor network. The chip has an 8-bit input register and an 8-bit DAC register, forming a two-stage buffer structure. This allows the DAC to output the previous data while simultaneously transferring the next data to the 8-bit input register, thus improving the speed of the digital-to-analog conversion. The interface circuit between DAC0832 and 80C51 is shown in Figure 3. The P0 port of the 80C51 is directly connected to the digital inputs DI7~DI0 of the DAC0832. The WR pin of the 80C51 is connected to the WR1 pin of the DAC0832. P2.7 is connected to the chip select pin CS. The chip uses a single-buffered configuration. The chip address is 7FFFH. 3.4 System Clock Generation The system clock can be generated using the timer/counter of the 80C51. The clock frequency is determined based on the highest output frequency; generally, fc ≥ 4f0max, and the cutoff frequency of the low-pass filter is the highest output frequency. In this design, the clock frequency requirement is 50 kHz, so a 20μs square wave output from the timer is used. The timer/counter T0 is selected, operating in mode 0, with the output pin P2.0. The 20μs square wave can be formed by alternating high and low levels with 10μs intervals; therefore, P2.0 only needs to be inverted every 10μs. Since the clock frequency of the 80C51 used in the experiment is 12 MHz, the initial count value is: X = 8192 - (10μs × 12MHz / 12) = 8192 - 10 = 8182. 4. Conclusion A clear sine wave can be observed on the oscilloscope. By changing the frequency code k using a computer, waveforms of different frequencies can be obtained, and the output frequency increases with the increase of the frequency control word. However, when the output frequency exceeds 13 kHz, the output waveform becomes significantly distorted, mainly due to spurious signals generated by the D/A conversion and low-pass filtering. Because the DDFS uses a fully digital structure, spurious signals are inevitably introduced. These spurious signals mainly originate from three sources: spurious signals caused by phase rounding errors in the phase accumulator, spurious signals caused by amplitude quantization errors (caused by the finite word length of the memory), and spurious signals caused by the non-ideal characteristics of the DAC. This design uses the generation of a sine wave as an example. In reality, as long as different waveform data are stored in the waveform memory of the DDFS, various waveform outputs can be achieved, such as triangular waves, sawtooth waves, rectangular waves, and even arbitrary waveforms. Furthermore, by adding corresponding controls within the DDFS, such as frequency modulation (FM), phase modulation (PM), and amplitude modulation (AM), frequency modulation, phase modulation, and amplitude modulation functions can be easily and flexibly implemented to generate FSK, PSK, ASK, and MSK signals. This has broad application prospects in fields such as communications, radar, electronic countermeasures, navigation, broadcasting, remote control and telemetry, and instrumentation.