I. Full Custom and Semi-Custom ASIC Chips
(I) Full Customization Design
This method is particularly suitable for analog circuits, mixed-signal circuits, and applications with special requirements for speed, power consumption, die area, and other device characteristics (such as linearity, symmetry, current capacity, and withstand voltage); or in situations where there is no readily available component library. Characteristics: meticulous craftsmanship, high design requirements, long design cycle, and high design cost.
As cell libraries and functional module circuits become more mature, full-custom design methods are gradually being replaced by semi-custom methods. In IC design, the phenomenon of using full-custom design for the entire circuit is becoming increasingly rare. Full-custom design requires consideration of process conditions, determining the device process type, number of wiring layers, material parameters, process methods, limiting parameters, yield, and other factors based on the complexity and difficulty of the circuit. It requires experience and skill, mastering various design rules and methods, and is generally completed by professional microelectronics IC designers. Conventional designs can draw on previous designs, while some components require individual design based on their electrical characteristics. Layout, routing, and arrangement combinations all require repeated consideration and adjustment, designing the layout according to principles such as optimal size, most reasonable layout, shortest interconnections, and most convenient pins. Layout design is process-dependent; a thorough understanding of process specifications is essential, and the layout and process must be designed rationally based on process parameters and requirements.
(II) Semi-custom design method
Semi-custom design methods are further divided into standard cell-based design methods and gate array-based design methods.
The standard cell-based design method involves arranging pre-designed logic units, such as AND gates, OR gates, multiplexers, and flip-flops, according to a specific rule, together with pre-designed large cells to form an ASIC. Standard cell-based ASICs are also known as CBICs (Cell-based ICs).
Gate array-based design methods involve designing application-specific integrated circuits (ASICs) on a pre-defined substrate or master chip with transistor arrays using mask interconnects. Compared to full-custom design, semi-custom design can shorten development cycles and reduce development costs and risks.
II. Design Process
(1) It is necessary to divide the ASIC into internal functional modules so that each functional module can perform the corresponding function. The functional modules are connected together to form the entire ASIC circuit.
(2) Based on the division of functional modules, according to the functional and interface requirements, the logic design of the modules is carried out using Hardware Description Language (HDL) to form Register Transfer Level (RTL) code.
(3) For the functional and timing requirements of the ASIC specification, use field-programmable gate array (FPGA) prototype or software simulation to write test code or test stimuli to perform logic verification and ensure that the logic design fully meets the design requirements.
(4) Map the RTL code to the corresponding process library through logic synthesis tools, perform layout design such as placement and routing, complete timing verification and convergence, and form layout data for wafer fabrication.
III. The Emergence of Structured ASIC
FPGA and ASIC each have their own advantages, and the academic community has also begun to explore technologies that combine ASIC and FPGA.
Intel introduced the concept of Structured ASIC. Structured ASIC is an incremental step between FPGA and cell-based ASIC. Structured ASIC starts with a common base array of logic, memory, I/O, transceivers, and hard-core processor systems. Designers only need to customize the interconnects, skipping many steps involved in the cell-based ASIC design flow, and instead focus on implementing the desired custom functionality.
Essentially, structured ASICs offer lower power consumption and lower unit cost compared to FPGAs, and lower NRE and faster time-to-market compared to cell-based ASICs.
In scientific research, we are happy to see a hundred schools of thought contending. Whether it is FPGA or ASIC, they both represent the ever-increasing possibilities of technology.
