At the heart of these IoT devices is ubiquitous cloud computing and machine learning, processes enabled by connectivity that require internet access to exchange vast amounts of information. While IoT devices have been part of the technology landscape for some time, it is their connection to the cloud that reveals the potential for exponential growth.
However, a core challenge for chip designers is that consumers now expect a cycle of innovation that continuously reduces costs, and they want their IoT devices to be increasingly compact and responsive. These demands force chip designers to make tough decisions, compromising on critical features such as connectivity, personalization, and sensor processing, all in order to achieve sufficient battery life within specific cost targets.
Today, design teams are exploring various avenues to develop devices with architectures that support multiple wireless connectivity standards, promote optimal power efficiency, and provide additional value, such as enhanced AI decision-making capabilities. This has led to the adoption of additional power-saving techniques that some industries have used for decades, but which were previously prohibitively expensive for the vast majority of SoCs.
Globally, companies are developing additional features and functionalities for the portable gadgets we use every day. A key differentiator for the success of these products is improved battery life by reducing power consumption for complex processing tasks.
Inside IoT edge devices, the underlying chips perform three main functions: sensing, processing, and communication. The renewed interest in low-power designs is driven by the increasing market demand for high performance, long battery life, and mobility in IoT devices.
Fundamentally, the goal of low-power design is to minimize both the dynamic and static components of power consumption. Each of these power components is directly related to factors such as frequency, peak current, and voltage. To achieve optimal performance while consuming minimal power, various low-power technologies and methods are needed to test every compromise among these factors to meet ever-growing market demands.
There are several approaches to developing low-power designs.
- Multi-voltage domains. Through this process, the chip's operating elements are assigned to various voltage domain blocks, depending on performance characteristics. Instead of categorizing entire regions as high-performance, the design helps determine the specific chip layout and which regions require higher voltages to function properly.
- Power supply gating. Functions within an integrated circuit are divided into different blocks based on their power domain, similar to a multi-voltage approach. Essentially, this completely shuts off the power to a block, thus saving both static and dynamic power.
- Register preservation. In this technique, whether it's a subset or all subsets of a block, their previous values are preserved when the block is closed; these values are restored when it's opened. This improves overall wake-up time and saves power by reducing the time and steps required to restore the original state. This approach is often used in conjunction with power gating techniques.
- Clock gating. By reducing overall switching activity and the need for multiplexers, clock gating reduces the dynamic power used and saves significant area.
In addition to the low-power design methods mentioned above, effective management of compressed artificial intelligence algorithms is also required. These algorithms may offer less flexibility and accuracy, but consume significantly less power. This shift has transformed the IoT design landscape and revolutionized power-related design processes as hardware and software co-design becomes more prevalent.
To address the world’s desire for instant connectivity, increased mobility, and the growing deployment of artificial intelligence, companies will have to invest in upgraded SoC design technologies, design optimization, and customization tools to model systems with specific IP hardware and software.
The IoT design roadmap will enhance operational efficiency, which may delay cost reductions for the next generation, but will clearly bring significant value to users.
