Abstract: This paper introduces the main features and structural functions of Altera's APEX20K series of multi-core programmable logic devices, and provides typical application examples of the ClockLock and ClockBoost circuits integrated into the APEX20K. Keywords: Programmable logic device, System design, FPGA, APEX20K 1. Main Features The APEX20K is Altera's first programmable logic device with a multi-core architecture, boasting a density of 30,000 to 1,500,000 gates and a clock speed of up to 822MHz. This multi-core structure overcomes the cumbersome process of implementing system-level designs using multiple devices, while also saving PCB space. Due to its advantages such as low power consumption, small size, high integration, high speed, low cost, user-definable functions, and reprogrammable and rewritable capabilities, the APEX20K can be widely used in system-on-board design. The APEX20K's key features are as follows: ● It is the first programmable logic device with a multi-core architecture; ● It includes an embedded system module and can implement various memory functions, including FIFO, dual-port RAM, and CAM (Content Addressable Memory); ● High density, high gate count, up to 51,840 logic elements, up to 442,368 RAM bits, and up to 3,456 multi-core product terms, thus meeting the high-density requirements of system-level designs; ● Low power consumption, operating on 1.8V-2.5V and interfacing with devices powered by 1.8V, 2.5V, 3.3V, and 5.0V; ● It features four phase-locked loop (PLL) circuits, providing clock locking, clock management, and clock shifting functions, thus reducing clock latency and jitter, and providing clock multiplication from 1x to 60x and division from 1x to 256, as well as programmable clock phase and delay phase shift; ● It has powerful I/O functions, and is compatible with PCIe... Compatible with SIG local bus standard peripherals, supporting Low Voltage Differential Signaling (LVDS), LVTTL, LVCMOS, GTL+, CTT, AGP, LVPECL, SSTL-3 and SSTL-2, and high-speed termination logic (HSTL Class I); ● Compatible with 64-bit, 64MHz PCI, supporting PCI-X; ● Supports high-speed external memory, including DDR SDRAM and ZBT SRAM; ● Operates at multiple voltages, ideal for use in mixed-voltage systems; ● Uses FineLine BGA packaging, reducing chip footprint and providing better temperature characteristics; ● Embedded with a SignalTap logic analyzer, enhancing chip functional verification performance; ● Supports the autorouting function of Altera's Quartus™ II development system. 2. Functional Description The APEX20K series devices integrate lookup table logic, product term logic, and memory into a single unit. Its 4-input lookup table function enables complex digital signal processing functions, and the product terms can be used to implement high-speed control logic and state machines. Each IOE in the APEX20K series includes a bidirectional I/O buffer and a register. IOEs can be used as input pins, output pins, and bidirectional pins. The APEX20K provides two dedicated clock pins and four dedicated input pins to drive register control inputs, generating a high-speed, low-distortion clock distribution. They use dedicated routing channels with very low latency. Four dedicated signals drive global signals, which can also be driven by internal logic to generate a high-fan-out asynchronous clear signal. The APEX20K series also offers ClockLock, ClockBoost, and Clockshift clock management circuitry. The APEX20K series consists of a series of MegaLAB structures, each containing 16 logic array blocks (LABs), an ESB, and a MegaLAB interconnect. Each LAB contains 10 logic elements (LEs), along with carry chains and stack chains associated with the LEs. Each LE can drive an additional 29 LEs via high-speed local interconnects. Each LE contains a 4-input lookup table. In addition, each LE contains a programmable register, a carry chain, and a stack chain. Each LE drives the local interconnect, MegaLAB interconnect, and FastTrack interconnect wiring structure. The APEX20K series device architecture provides two types of dedicated high-speed data channels, carry chain and stack chain, which can be used to connect adjacent LEs. This connection does not use the local interconnect channel, but only the carry chain to perform adders, counters, and comparators (which can be automatically used by software tools and Mega functions). The dedicated stack chain can perform high-speed, high-fan-out logic functions. (1) Normal operation mode This mode utilizes its internal stack chain and is suitable for general logic applications, combinational functions, or wideband decoding functions. In this mode, four data inputs from the LAB local interconnect and carry input are fed into a four-input LUT. (2) Arithmetic mode This mode is suitable for adder, accumulator, and comparator applications. In arithmetic mode, one LE uses two 3-input LUTs. The first LUT uses the carry input signal and input data to generate a combined output. The second LUT uses this combined signal to generate a carry output, thereby forming a carry chain. (3) Counting Mode This mode provides clock enable, count enable, synchronous increment/decrement control, synchronous clear, and synchronous load selection. Synchronous clear and synchronous load are LAB wide signals that affect the LAB registers. Therefore, if any LAB is operating in counting mode, the remaining LEs in the LAB are used as part of the same counter or for composite functions. Counting mode utilizes two three-input LUTs, one for counting data and the other for generating a fast carry bit. A 2-to-1 multiplexer provides synchronous load, and another AND gate provides asynchronous clear. All 20K devices can be reconfigured on boards for special purpose applications. The APEX20K can be programmed in-system via serial data charge using configuration chips EPC1, EPC2, and EPC16. Therefore, the APEX20K includes an optional interface that allows the APEX20K microprocessor to configure the chip serially or in parallel, synchronously or asynchronously. Thus, the microprocessor can treat the APEX20K as memory and configure the device by writing to virtual memory, and configuration is very easy. After the APEX20K device is configured, new data can be loaded by resetting the device. 3. Application Examples The APEX20K series devices support clock management functions such as ClockLock and ClockBoost, which are guaranteed by a PLL. The ClockLock circuit uses a synchronous PLL to reduce internal clock delay and distortion. The ClockBoost circuit can multiply the clock. It has an internal high-speed clock distribution tree, and designers do not need to design and optimize the clock distribution tree. When designing the circuit board, a low-frequency signal can be used as the input clock, and then multiplied on-chip to become a high-frequency clock. Because using a low-frequency clock reduces transmission line interference and simplifies the circuit board layout. The APEX20K can perform 2x or 4x multiplication, while the APEX20KE can perform more complex multiplication. 3.1 Application of Frequency Multiplier Circuits In microprocessor-based applications, the system's input clock frequency can be lower than the clock frequencies of other devices in the system. An embedded microprocessor or its peripheral circuits can operate at a faster rate than the I/O bus clock. Since fast clocks are required for synchronization or counting in embedded applications, the clock management circuitry in the APEX20K is frequently used to multiply low-frequency bus clocks and can be used in-system development. 3.2 Reducing On-Board Clock Delay The feedback pins of the APEX20KE series devices can reduce clock distortion between devices on the board. The PLL function can connect the feedback input to the CLK input. The PLL can dynamically adjust output changes due to temperature or voltage variations during operation. Therefore, during board design, the delay of the feedback input should match the delay generated by each device involved. Identical delays ensure synchronization between the feedback input and the target device, thus eliminating delay. During board routing design, the path from CLKLK-OUT1 to each device should be equal to the path from the feedback to CLKLK-FB1. 4. Conclusion Utilizing the advanced ClockLock and ClockBoost functions of the APEX20K series can significantly improve system performance and design flexibility. It can also reduce clock latency and eliminate clock distortion within the device. ClockBoost simplifies board design and allows for logic operations at frequencies much higher than the input clock frequency to be performed internally. Furthermore, the APEX20KE series devices can perform frequency multiplication by m/(n)×k, where m and k range from 2 to 160, and n ranges from 1 to 16. Its LVDS I/O interface and phase adjustment enable more complex clock synthesis processing. The APEX20K series devices support many voltage standards, and in particular, its LVDS performance can reach 822M/s with strong immunity to board-level noise and very low power consumption. Using LVDS as an I/O interface solution is gradually becoming a trend. Therefore, the APEX20K series devices will be applied in more and more fields.