The first hurdle is the architectural design.
Chip design involves numerous steps, each presenting many challenges. Taking the relatively simpler digital integrated circuit design as an example, the design process often employs a top-down approach, breaking down the design into layers that include:
Demand Definition: Combining external environment analysis, supply chain resources, and the company's own positioning, we propose requirements for the next-generation product, further considering the product's role, function, required number of circuit boards, and type of integrated circuits used, to accurately define product requirements. The difficulty of this stage lies in accurately judging future market and technological trends and having a thorough understanding of the situation and capabilities of designers, manufacturing plants, and the entire industry chain.
Functionality Implementation: This describes the goals the chip needs to achieve, typically written in a hardware description language. The difficulty in this stage lies in understanding the overall performance and functionality achievable by the chip, ensuring that the goals are fully met without exceeding its own capabilities.
Structural design: Based on the characteristics of the chip, it is divided into sub-modules with clear interfaces, well-defined interrelationships, and relatively independent functions. The difficulty in this step lies in familiarity with the chip structure and whether the requirements can be met with as few modules as possible and with the lowest possible standards.
Logic synthesis: Developers translate hardware description languages into logic circuit diagrams. The challenge in this step lies in ensuring that the code is synthesizable, clear, concise, and readable, and sometimes also considering module reusability.
Physical implementation: Transforming the logic circuit into a circuit diagram with physical connections. The challenge of this step lies in how to map from the RTL description to the synthesis library cells using as few components and connections as possible, based on the manufacturing process, to obtain a gate-level netlist that meets the requirements in terms of area and timing, while ensuring that the internal components do not interfere with each other.
Physical layout: The GDSII file format is given to the wafer fab to create the actual circuitry on the silicon wafer, followed by packaging and testing to obtain the physical chip.
It must be noted that chip design involves considering many variables, such as signal interference and heat distribution. The physical characteristics of a chip, such as magnetic fields and signal interference, vary significantly across different manufacturing processes. There are no mathematical formulas for direct calculation, nor are there readily applicable empirical data to input. The design must be carried out step-by-step using EDA tools, involving continuous design, simulation, and trade-offs. If the results are unsatisfactory after each simulation, the design must be reworked, posing a significant challenge to the team's intelligence, energy, and patience.
The second hurdle lies in verification.
The goal of chip verification is to repeatedly verify the chip before it is manufactured through methods such as inspection, simulation, and prototyping platforms, in order to discover system software and hardware functional errors in advance, optimize performance and power consumption, and make the design accurate, reliable, and in line with the originally planned chip specifications.
It is not a process performed after the design is completed, but a repetitive behavior that runs through every stage of the design process. It can be further divided into system-level verification, hardware logic function verification, mixed-signal verification, software function verification, physical layer verification, timing verification, etc.
Verification is difficult. First, verification can only falsify, and it requires repeated consideration of possible problems and the use of formal verification and other methods to ensure the probability of correctness. It is a great test of the designer's experience and wisdom.
Secondly, the verification methods must be as efficient as possible. Modern chips integrate microprocessors, analog IP cores, digital IP cores, and memory (or off-chip memory control interfaces), leading to an exponential increase in verification complexity. How to quickly, accurately, completely, and easily debug these increasingly complex verifications to reach the tape-out stage is the biggest challenge for every chip designer.
Finally, let's look at the verification tools themselves. Taking common FPGA hardware simulation verification as an example, in the 1990s, FPGA verification could support up to 2 million gates, with each gate costing $1. Although the unit price has dropped significantly today, with the exponential increase in chip complexity, the number of gates to be verified has risen to the scale of tens or hundreds of millions, making the overall cost even more staggering.
Furthermore, FPGA itself is a type of chip design. Nowadays, large-scale designs (more than 20 million equivalent ASIC gates) require the interconnection of multiple FPGAs for verification. FPGA design faces practical requirements such as RTL logic partitioning, interconnection topology between multiple FPGAs, I/O allocation, placement and routing, and observability, which further increases the difficulty of the design process.
