Understanding the key challenges of designing power solutions for today's high-resolution, high-frame-rate CMOS image sensors is crucial for designing an optimized power system solution with an LDO (DC-DC, PMIC) that meets the requirements of every design engineer. Power system designers need to know how power solutions differ across applications—for example, how the power solution for an 8-megapixel (MP) camera differs from that for a 50-megapixel camera—or how different frame rates (30fps, 60fps, 120fps) change their power design, at what frequency a high power supply rejection ratio (PSRR) is required, and so on. This article aims to highlight the fundamental considerations before determining a power solution for any image sensor today.
Foreword
Every CMOS imaging system contains an active pixel region and a photodetector. The photodetector captures photons and converts them into a very small photocurrent or electron. Different parts read the data, including the ADC, analog signal processing, user interface digital logic, timing, etc. Within the femtoamp range, a small amount of photodiode current is integrated into a small charge during the exposure time (when the shutter is open), which is then converted into a readable voltage by the ADC.
Figure 1. Typical CMOS imager structure
Pixel, resolution and transistor design
Each pixel also has a fill factor, depending on the percentage of the total pixel area used, and is divided into two parts: a photosensitive part and a non-photosensitive part. The photosensitive area captures light, while the non-photosensitive area is used for the ADC, digital block, interface, and other functions. The remaining area is used for horizontal or vertical readout, where a typical READ or WRITE sequence is initiated by the host, generating a start condition on the bus. The resolution of a CMOS image sensor is the total number of pixels in the pixel array, which consists of many columns and rows. For example, a typical 2-megapixel camera pixel array might be 1600x1200.
Figure 2. List of common camera pixels
Some pixels in columns and rows are called dark pixels. They are optically black and are used internally for black level correction or row noise correction. This results in a reduction in the actual active pixel array or the actual effective pixels in the array.
There are many different pixel transistor designs (3T, 4T, 5T), such as the four-transistor (4T) pixel design shown below. The photodiode converts received photons into a small amount of charge, and there are switches used to select different columns and rows. To avoid interfering with the photodiode readings, a high-impedance amplifier at the photodiode junction is used as a source follower amplifier (TIA/SIA).
(TIA/SFAmp) is used to drive each column of buses.
Figure 3. Example of a four-transistor design
The voltage of each pixel is read one row at a time and placed into the column capacitor (Cs), and then read using a column decoder and multiplexer.
Figure 4. Example frames and row transformations for selected rows and columns.
Frame rate measures the speed at which a complete image is captured and read out of the array for processing; a typical frequency range is 30-120 Hz. Image sensors can be high frame rate devices (>60 fps) for slow-motion playback or low frame rate devices (<60 fps) for motion blur effects.
The rate of return (PSRR) can also be limited or affected by shutter speed, which controls the amount of time the image sensor collects light, or the programmable time interval known as the "dark period" that occurs after the last line is used for horizontal blanking, synchronization time, or other purposes. We can calculate the frequency of the highest PSRR required for a given frame rate (15, 30, or 60) -- for example, a 4-megapixel camera -- and design an LDO with the required PSRR to calculate the frequency.
Figure 5. Effect of different frame rates on horizontal frequency
The frame rate is approximately 75% of the readout rate, with the remaining 25% reserved for other processing tasks such as aperture adjustments, exposure time calculations, lens autofocus (AF), image processing, and memory write speed. For still images and videos, frame readout is performed line by line, and finally, the entire frame is collected in the buffer to present the complete image.
Image sensor power rail
CMOS image sensors typically require three different power rails to power the analog rail (AVDD), the interface rail (DOVDD), and the digital rail (DVDD). The standard voltage for the analog power rail is 2.8V, the interface power rail is 2.8V or 1.8V, and the digital power rail is 1.8V or 1.2V.
To improve the noise performance of a CMOS image sensor, a large bypass capacitor can be placed before the power supply pins. Reducing the ripple of each power rail also improves the noise performance of the CMOS image sensor. Generally, analog power rails are the most noise-sensitive rails, followed by digital rails, which are also quite sensitive to noise.
Power Supply Rejection Ratio (PSRR)
PSRR provides a way to measure an LDO's ability to suppress ripple, or how well it blocks noise generated solely by the power rails at the LDO's input. A higher PSRR means it blocks more power supply noise or ripple. This ripple can originate from a 50/60Hz ripple input power supply, the switching frequency of a DC-DC converter, or ripple generated due to different circuits sharing the input power supply.
Figure 6. Example of noise from LDO input to output.
The feedback loop of an LDO typically controls the PSRR of a system below 100kHz. Therefore, it is important to ensure that a suitable LDO is selected. For frequencies above 100kHz, appropriate selection of passive components and PCB layout/location are used to control PSRR.
Figure 7. Relationship between PSRR behavior and frequency of a typical LDO
When designing the PCB, attention should be paid to ensuring tight current loops to reduce parasitic inductance and ripple between the power rail and the camera rail. Using a clean bias or a higher margin between Vin and Vo can also increase PSRR performance.
Low PSRR performance or any noise on the analog rails can cause noise on the power rails to enter the output signal path through the high-gain source follower amplifier circuitry, resulting in unwanted horizontal ripples in the captured image.
Figure 8. Noise example on the simulated track
Ordinary LDOs have low PSRR at high frequencies, which should be sufficient for ordinary cameras. However, for high-resolution and high-frame-rate image sensors in the 50-200MP range, specific series of LDOs are definitely needed, with PSRR greater than 90dB at lower frequency ranges (up to 10kHz) and PSRR greater than 45dB in the 1-3MHz frequency range, to reduce ripple during frame and line rate conversion.
Relationship between sensor frame and line rates and power load
It is worth noting that both frame rate (30-120fps) and line rate (22-44kHz) impose dynamic loads on the image sensor, producing undershoot and overshoot on the 2.8V analog rail.
During each new frame or line transition, the current draw is like a stepped load. For example, during a frame or line read, or between each frame or line read, the power supply scheme (LDO) needs to handle a load change of several hundred milliamps during each frame and line transition, but without any significant fluctuations on its output voltage rail.
For camera decoupling, the bulk capacitor needs to have the lowest impedance near the line and frame frequencies to achieve optimal system performance.
LDO output noise (μVRMS)
Depending on the design of the image sensor, each pixel has a charge saturation or full-well capacity—the amount of charge (in electrons) a pixel can hold before it saturates. For any image sensor, dynamic range (dB) is defined as the brightest and darkest parts of an image that can be captured simultaneously.
Figure 9. Examples of pixel capacity and background noise.
At the output of any LDO, the lower the spectral noise density between 10 Hz and 1 MHz, the more important it is to transfer less noise to the CMOS image sensor, thus resulting in a higher dynamic range for a given pixel.
Figure 10 Typical LDO output noise density
Finding the signal-to-noise ratio (SNR) information of the CMOS image sensor and designing the system is crucial to ensure that the overall ripple and noise are at least 40 dB lower than the sensor's noise threshold.
Summarize
Designing LDO power solutions for image sensors of different specifications presents various challenges, such as 4-megapixel versus 40-megapixel, 30fps versus 120fps, or high dynamic range versus low dynamic range, and so on. We achieve the maximum permissible frame rate for high-resolution cameras by leveraging the maximum data rate capabilities provided by the Internet Service Provider (ISP) and the number of C/D-PHYMIPI channels used. Considering the highest PSRR required for the calculated maximum frame rate frequency, and the RMS noise density required for a given image sensor along with the known SNR, we can design an optimized power system to meet the requirements of today's high-resolution and high-frame-rate CMOS image sensors.
Using an LDO scheme with high PSRR and low RMS noise at higher frequencies, along with suitable passive devices with specific impedances at given vertical and horizontal frequencies, can help improve the overall noise performance of CMOS image sensors, reduce power supply ripple, and thus reduce unwanted horizontal ripple in captured images.
