Placing multiple chips side-by-side in the same package can alleviate thermal issues, but as companies delve deeper into chip stacking and denser packaging to improve performance and reduce power consumption, they are grappling with a host of new heat-related problems.
Advanced packaged chips not only meet the demands of high-performance computing, artificial intelligence, and increased power density, but also complicate heat dissipation issues. This is because hotspots on one chip can affect the heat distribution of neighboring chips. Furthermore, the interconnect speed between chips is slower in modules than in SoCs.
John Parry, head of electronics and semiconductors at Siemens Digital Industries Software, said: "Before the world moved into areas like multi-core, you were dealing with a single chip with a maximum power of about 150 watts per square centimeter, which was a single-point heat source. You could dissipate heat in all three directions, so you could achieve some fairly high power density. But when you have one chip, put another chip next to it, and then put another chip next to it, they heat each other up. This means you can't tolerate every chip having the same power level, which makes the thermal challenges much more difficult."
This is one of the main reasons why 3D-IC stacking has progressed slowly in the market. While the concept makes sense from a power efficiency and integration perspective—it works well in 3D NAND and HBM—it's a different story when logic is involved. Logic chips generate heat, and the denser the logic and the higher the utilization of the processed elements, the more heat is generated. This makes logic stacking rare, which explains the popularity of 2.5D flip-chip BGAs and fan-out designs (see Figure 1).
Figure 1: To meet power density, bandwidth, and heat dissipation requirements, the high-density VIPack platform includes RDL and TSV-based interconnects in six architectures. Source: ASE.
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For chip designers, there are many packaging methods available. However, the performance of chip integration is crucial. Components such as silicon, TSV, and copper pillars have different coefficients of thermal expansion (TCE), which affect assembly yield and long-term reliability.
If you're going to turn the circuit on and off at a higher frequency, you might encounter thermal cycling issues. Printed circuit boards, solder balls, and silicon all expand and contract at different rates. Therefore, it's common to see thermal cycling failures in the corners of the package, where solder balls may crack. This may necessitate installing additional ground wires or power supplies there.
The currently popular flip-chip BGA package with CPU and HBM has an area of approximately 2500 square millimeters. Mike McIntyre, Director of Software Product Management at Onto Innovation, said, "We see a large chip potentially becoming four or five smaller chips. So there must be more I/O for these chips to communicate with each other. Therefore, you can distribute the heat."
Ultimately, heat dissipation is a problem that can only be addressed at the system level, and it involves a series of trade-offs.
In fact, some devices are so complex that it is difficult to easily replace components to customize these devices for specific applications. This is why many advanced packaging products are used for components with very high volume or price flexibility, such as server chips.
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Nevertheless, engineers are exploring new methods for performing thermal analysis of package reliability prior to module fabrication. For example, Siemens offers a dual-ASIC-based module that mounts a fan-out redistribution layer (RDL) on a multilayer organic substrate in a BGA package. It uses two models: one for the RDL-based WLP and another for the BGA on the multilayer organic substrate. These package models are parameterized, including the substrate layer stack and BGA before EDA information is incorporated, enabling early material evaluation and chip placement selection. Next, EDA data is imported, and for each model, material maps provide a detailed thermal description of the copper distribution across all layers. The final thermal dissipation simulation (see Figure 2) considers all materials except for the metal cap, TIM, and underfill.
Figure 2: Thermal models of two ASICs, using separate thermal models of an RDL fan-out WLP and an organic BGA, showing top and cross-sectional views of heat rising through the substrate and interconnects towards the metal cap. Source: Siemens
Eric Ouyang, Technical Marketing Director at JCET, along with engineers from JCET and Meta, compared the thermal performance of monolithic chips, multi-chip modules, 2.5D through-hole boards, and 3D stacked chips with an ASIC and two SRAMs. The Apple-to-Apple comparison kept server environments, heatsinks with vacuum chambers, and TIMs constant. Thermally, 2.5D and MCMs outperformed 3D or monolithic chips. Ouyang and his colleagues at JCET designed a resistor matrix and power envelope plot (see Figure 3) that can be used in early module design to determine whether the input power levels and set junction temperatures of different chips can be reliably combined before time-consuming thermal simulations. As shown in the figure, a safety region highlights the power range on each chip that meets reliability standards.
Ouyang explained that during the design process, circuit designers may have an idea of the power levels of the various chips placed in a module, but may not know whether those power levels are within reliable limits. This diagram defines the safe power range for up to three chips in a small chip module. The team has developed an automatic power calculator for more chips.
Figure 3: In a 2.5D liner layout, the red area represents the safe power level for one ASIC and two SRAM chips, maintaining Tj-Ta < 95°C. Source: JCET
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We can understand how heat is conducted through silicon chips, circuit boards, adhesives, TIMs, or package caps, while using standard methods such as temperature difference and power functions to track temperature and resistance values.
"JCET's Ouyang said, 'The thermal path is quantified by three key values—the thermal resistance from the device junction to the environment, the thermal resistance from the junction to the case [on top of the package], and the thermal resistance from the junction to the board.' He noted that, at a minimum, JCET's customers require θja, θjc, and θjb before they use them in their system designs. They might require a given thermal resistance not exceeding a specific value and require the package design to provide that performance. (See JEDEC's JESD51-12. Report and Guidelines for Using Package Thermal Information for details.)'"
Figure 4: Thermal resistance from chip to package to circuit board quantifies the heat dissipation capability of the package. Source: JCET
Thermal simulation is the most economical method for exploring material selection and matching. By simulating the chip in its operating state, we can typically identify one or more hot spots. Therefore, we can add copper to the substrate beneath the hot spots to facilitate heat dissipation; or change the packaging material and add a heatsink. System integrators may specify that the thermal resistances θja, θjc, and θjb must not exceed certain values. Typically, the silicon junction temperature should be kept below 125°C.
After the simulation is completed, the packaging manufacturer conducts a Design of Experiments (DOE) to derive the final packaging solution.
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In the package, over 90% of the heat is dissipated from the top of the chip to the heatsink, typically vertical fins based on anodized aluminum. A thermal interface material (TIM) with high thermal conductivity is placed between the chip and the package to aid in heat transfer. Next-generation TIMs for CPUs include sheet metal alloys (such as indium and tin) and silver-sintered tin, with conductivity of 60 W/mK and 50 W/mK, respectively.
As manufacturers transition SoCs to chiplet processes, there is a greater need for TIMs with different properties and thicknesses.
YoungDo Kweon, Senior Director of R&D at Amkor, stated that for high-density systems, the thermal resistance of the junction interface material (TIM) between the chip and the package has a greater impact on the overall thermal resistance of the package module. Power trends are increasing dramatically, especially for logic, so we are focused on maintaining low junction temperatures to ensure reliable semiconductor operation. While TIM suppliers provide thermal resistance values for their materials, the actual thermal resistance (θjc) from chip to package is affected by the assembly process itself, including the bonding quality and contact area between the chip and the TIM. He pointed out that testing in a controlled environment with actual assembly tools and adhesive materials is crucial for understanding actual thermal performance and selecting the optimal TIM for customer qualification.
Voids are a particular issue. Siemens' Parry stated, "The application of materials in encapsulation is a major challenge. We already know that the material properties of adhesives or glues, and how the material wets the surface, affect the overall thermal resistance exhibited by the material, i.e., contact resistance. This largely depends on how the material flows into the surface without creating defects. If there are gaps that are not filled by the adhesive, they will create additional resistance to heat flow."
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Chipmakers are grappling with heat dissipation issues. Randy White, Memory Solutions Program Manager at Keysight Technologies, says, “If you keep the packaging the same and shrink the chip size by a quarter, the speed increases. This can lead to some differences in signal integrity. Because the bonding wires from the external package go into the chip, the longer the wires, the greater the inductance, so there's an electrical aspect to that. So, how do you dissipate that much energy in a sufficiently small space? That's another key parameter that needs to be studied.”
This has led to significant investment in cutting-edge bonding research, seemingly focused on hybrid bonding. However, hybrid bonding is expensive and remains limited to high-performance processor applications; TSMC is currently one of the only companies offering this technology. Nevertheless, the prospect of combining photons on CMOS chips or silicon-based gallium nitride is promising.
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The initial idea behind advanced packaging was that it would work like Lego bricks—chips developed at different process nodes could be assembled together, mitigating thermal issues. But this comes at a cost. From a performance and power perspective, the distance signals need to travel is critical, and having circuits always on, or needing to remain partially on, impacts thermal performance. Dividing chips into multiple parts to improve yield and flexibility is not as simple as it seems. Every interconnect within the package must be optimized, and hotspots are no longer confined to a single chip.
Early modeling tools allowed for the elimination of different chip combinations, providing significant impetus for designers of complex modules. In this era of ever-increasing power density, thermal simulation and the introduction of new TIMs will remain essential.
