Abstract : This paper introduces a novel PowerPC440GP 32-bit high-performance microcontroller, proposes a hardware design scheme for an embedded network server system based on the PowerPC440GP, and provides some design details. Then, it discusses the development, porting, and BSP bootloader development process of the VxWorks embedded operating system based on this hardware platform. Keywords : Reduced Instruction Set Computer (RISC); PowerPC440GP; VxWorks BSP; BootROM 1 Introduction The PowerPC440GP is a high-performance 32-bit RISC embedded processor launched by IBM. It integrates the PowerPC440 core and various rich peripheral device interface resources on-chip, with a maximum speed of 500 MHz, making it suitable for embedded products such as desktop devices like switches, routers, and network servers. This paper proposes a relatively general application system design scheme for network servers based on the characteristics of this processor, and discusses the key software and hardware technologies of this scheme. 2. Features and Performance of the PowerPC440GP: A 128-bit Processor Local Bus (PLB) provides peak read/write speeds of 4.2 GB/s for accessing high-performance devices such as PCI and DDR SDRAM. It uses a 36-bit address path, providing 64 GB of memory addressing capability. A 32-bit On-Chip Peripheral Bus (OPB) connects to low-performance devices such as serial ports, Ethernet ports, external bus controllers, and I2C ports to improve PLB bus utilization. A 10-bit addressable DCR bus accesses the status and control registers of various master and slave devices on the PLB bus. It features a 64-bit on-chip Double Rate DDR SDRAM controller, providing up to four chip select signals. It has a 64-bit PCI interface with a maximum frequency of 133 MHz. A 32-bit external bus controller supports up to eight peripherals. Two 10 MB/s/100 MB/s on-chip Ethernet controllers. Two serial ports and two I2C ports. 32 general purpose input/output (GPIO) ports. 13 external interrupts and 45 internal interrupt resources. The CPU operating frequency can be selected through initialization configuration at 400 MHz, 466 MHz, and 500 MHz, with a typical power consumption of less than 4W. Power supply: logic voltage 1.8V, DDR SDRAM interface voltage 2.5V, I/O port voltage 3.3V. 3. Application System Design Scheme This network server platform is based on the PowerPC440GP processor, with necessary expansions. The system structure block diagram is shown in Figure 1. The system includes a PowerPC440GP processor and its power-on reset circuit, power supply circuit, system clock circuit, DDR memory and expansion circuit, program storage and boot/debugging Flash circuit, an EEPROM connected to the I2C bus for boot configuration, a JTAG port for ICE debugging, and communication interfaces such as Ethernet and serial ports. 3.1 Power Supply Circuit Design This system requires three power supplies: 1.8V, 2.5V, and 3.3V. A switching power supply provides a unified 3.3V power supply and ground plane. An LP3963ES-2.5 LDO is selected to provide 2.5V, and its maximum load current can reach 3A, which meets the system requirements. Using 2.5V as the input, a TPS77518 DC/DC converter is selected to provide 1.8V, effectively reducing the power loss of the secondary power supply. 3.2 CPU Clock Circuit Design This system uses a 33.33 MHz external crystal oscillator connected to the CPU's Sysclk pin as an external low-frequency clock source. The on-chip phase-locked loop (PLL) is then initialized to multiply the external low-frequency clock source, providing a high-frequency system clock. 3.3 DDR SDRAM Circuit Design Since the PowerPC440GP's DDR SDRAM interface has a maximum 64-bit data bus and 8-bit ECC error correction bits, five HY5DU281622ETP-M chips are selected as the on-board memory modules. This circuit structure is 8 M x ​​16 bits, with the five memory circuits sharing one bankSel0 chip select space. Four memory circuits form a 64-bit data storage area with a memory capacity of 64 MB. The lower 8 bits of the remaining memory circuit are used for ECC. One 184-pin DIMM (a 72-bit ECC memory module must be used) can also be added. The clock for each circuit in the memory module and the DIMM is provided by the PowerPC440GP's Memclkout0 pin (its frequency is equal to the PLB bus clock, typically 100 MHz or 133 MHz). To ensure clock synchronization of all devices... The CY2309 clock matching device is introduced. This device has an internal clock phase-locked loop (PLL) that can split the clock signal output from the pins into nine clock signals with identical phase and frequency (five for the chip and four for the DIMM), and can prevent the reflection of any clock signal from affecting other clocks. The DDR SDRAM module adopts the SSTL-2 signal standard and operates at 2.5V. When designing the board layout, key considerations should be given to the routing and length of signal lines such as Data/DM/DQS, the termination methods of the signal lines, and the circuit design of the termination voltage VTT and input reference voltage signal VREF that meet the SSTL-2 signal requirements. Data/DM/DQS signal lines should use the same routing structure as much as possible and strictly maintain equal length. Series-parallel termination is recommended for the signal line ends, as shown in Figure 2. Here, the resistance of the series termination resistor is generally 22 Ω, and the resistance of the parallel termination resistor is generally 25 Ω. The resistor should be placed as close as possible to the signal receiving pin to effectively reduce signal reflection and electromagnetic interference, and to accommodate higher clock rates. For the termination voltage VTT and reference voltage VREF, the ML6554 recommended by the memory manufacturer is used. Furthermore, due to the complexity of the timing operations of the DDR SDRAM circuit, board-level simulation of this part of the circuit, combined with the configuration of the controller's internal timing registers, is crucial. 3.4 Program Storage Circuit Design Since the PowerPC440GP's EBC bus has 32 data lines, two MX29LV160BTC Flash devices are selected to store the BSP, the real-time operating system VxWorks, and user applications. The Flash's BYTE pin is set high, enabling the Flash to operate in x16 mode. Thus, the two Flash devices share one CS0 chip select space, forming the high 16 bits and low 16 bits of the EBC data bus for synchronous access, with a capacity of 4MB. Because the PowerPC440GP uses a PowerPC core, meaning that A31 is the LSB and A0 is the MSB, and the data bus is also the same, while the Flash's A0 and DO are both LSBs, the pin order must be carefully considered during wiring. Additionally, since Flash performs 4-byte synchronous read operations, the CPU address lines should be shifted left by 2 bits during connection, meaning the least significant bits A0 and A1 are not used. For easier system debugging, a 512 KB SST39SF040 can be added for BootROM startup. It can be mutually selected with the two Flash chips via jumpers (CS0 chip select), so the system will automatically read the boot code from the CSO device during startup. The program storage module is shown in Figure 3. 3.5 Ethernet Interface Circuit Design An RTL8201BL network port circuit is used to implement the interface between the Power-PC440GP and a 100MHz Ethernet. An external 25MHz crystal oscillator is used, connected to the Ethernet via a 16PT8515 network filter, as shown in Figure 4. Since the PowerPC440GP has a 100MHz Ethernet MAC, it can achieve seamless connection with the RTL8201BL. The RTL8201BL has two interfaces: SNI and MII; this system uses MII. Interface selection can be achieved by setting the MII/SNIB pin to high level and correctly configuring the ANE, SPEED, and DUPLEX pins. The MII can operate at 25 MHz and 2.5 MHz frequencies, supporting 100 MHz Ethernet and 10 MHz Ethernet respectively. During data transmission, the MAC first determines the THEN signal and converts the 8-bit data to 4-bit data, then transmits it to the physical layer via TXD[0:3]. During the validity period of the TXEN signal, the PHY synchronously samples the data on TXD[0:3] using the transmission clock signal TXCLK. When receiving data, the PHY determines the receive enable signal to receive the data on RXD[0:3]. 3.6 System Startup Configuration The PowerPC440GP has one I2C bus startup configuration controller. This controller is enabled when the UARTO-DCD# pin is set to high level. An AT24C32 containing startup configuration information is connected to the I2C interface as a slave device. When the system powers on or resets, the controller can continuously read 16 bytes from the slave device located on the I2C0 interface. These 16 bytes of data are stored in four power-on configuration registers, CPC0-STRPO:3, used to initialize PLL settings, on-chip bus clock rates, startup location, startup width, and some user-defined configurations. If data reading fails or the UART0-DCD# pin is set low, these configurations will all use default values. The high or low setting of another configuration pin, UART0-DSR#, determines whether the 7-bit address of the I2C bus slave device is 0xA0 or 0xA8. 4. VxWorks Development and Porting This system uses the VxWorks embedded real-time operating system and its integrated development tool Tornado from Windriver. The system development and debugging tool uses the Vision-Ice emulator produced by Windriver. One end of the emulator is connected to the PC's network port, and the other end is connected to the JTAG interface of the PowerPC440GP. During development, the PowerPC kernel and external DDR SDRAM are debugged first. Once they are working correctly, the RTOS can be downloaded to memory via an emulator to assist in hardware debugging. Next, the network port is debugged. If the network port works correctly, the emulator can be discontinued, and tools provided by Tornado (such as WDB) can be used to establish a communication mechanism between the board and the PC via the network cable to debug other modules and develop applications. After the program development is complete, the correct boot code is burned into the BootROM. The BootROM bootloader then downloads and burns the VxWorks kernel and application to Flash memory via FTP. A key reason for VxWorks' widespread popularity is its portability. Through the Board Support Package (BSP), the VxWorks operating system's application code can be independent of the hardware. System porting only requires modifying the BSP according to the hardware platform; the operating system and applications do not need to be changed. 5. VxWorks BSP File Structure and Development Process In VxWorks, a BSP consists of a set of files related to a specific target system. These files include the makefile (compilation file), romInit.s (ROM initialization file), sysAlib.s (system initialization file), config.h (config configuration file), bspname.h (target board definition file), configNet.h (network configuration file), sysLib.c (system library file), usrConfig.c (user configuration file), bootConfig.c (boot configuration file), bootlnit.C (boot initialization file), sysSerial.c (serial port file), and ibmEmacEnd.c (Ethernet interface file), etc. The BSP startup process is shown in Figure 5. 5.1 Setting up the development environment mainly uses the development board CPU's BSP file as a template. Create a user's BSP directory bspname under the \tornado\target\config directory, and copy the files and BSP template files from \tornado\target\config\all to this directory. 5.2 Modifying Template Files 5.2.1 Makefile This file controls the creation of the image file via command line and must define the following macros: CPU: PowerPC440GP; TOOL: GNU; TGT_DIR: Path to the target board directory, use the default; TARGET_DIR: BSP directory name, customizable; VENDOR: Target manufacturer name, IBM; BOARD: Target board name, customizable; ROM_TEXT_ADRS: Entry address of the boot ROM, set to 0xfff80100 in this system; ROM_SIZE: ROM size, 512 KB in this system; RAM_LOW_ADRS: Target address for loading VxWorks, set to 0x00010000 in this system; RAM_HIGH_ADRS: Target address for copying the boot ROM image to RAM, set to 0x00C00000 in this system. 5.2.2 bspname.h This file configures the serial interface, clock, and I/O devices according to the PowerPC440GP, and must include the following: Interrupt vectors/priority levels; I/O device addresses; Meaning of each bit in the device registers; System and additional clock parameters (maximum and minimum rates). 5.2.3 config.h This file contains definitions for all components related to the PowerPC440GP target board. It sets the default boot line: use network boot; RAM address and size: address starts from 0, 64 MB size; ECC setting: enabled; MMU and Cache support: Cache supported; Timer external clock support: no; Serial port clock definition: use external clock; Serial port default channel: use channel 1; Ethernet port included: Ethernet interface supported; WDB default communication mode: Ethernet. Additionally, note that ROM_TEXT_ADRS, ROM_SIZE, RAM_LOW_ADRS, and RAM_HIGH_ADRS must be consistent with their definitions in the Makefile. 5.2.4 romInit.s This file contains assembly language initialization code. The romInit() function is the entry point for the BootROM and the ROM-based Vx-Works image. The tasks it performs include: clearing and setting relevant registers; disabling interrupts by setting the CE and EE bits in the MSR register; disabling data and instruction caches; initializing the EBC bus registers by allocating chip select signals and address space to various devices on the EBC bus by setting the bank registers; initializing memory by configuring the registers of the DDR SDRAM interface and allocating chip select signals and address space to the onboard memory and DIMMs. Note that the configuration of timing registers such as SDRAM0_TR1 and SDRAM0_WRDTR should be combined with the memory module routing simulation; initializing the stack pointer; calculating the address of the romStart() function, then jumping to that function to execute C language code without returning. 5.2.5 The user configuration file usrConfig.c contains the main initialization code for the VxWorks image, while the boot configuration file bootConfig.c contains the main initialization code for the bootrom image. bootInit.c is the second stage of ROM initialization. After RomInit() completes, it jumps to romStart() in this file, which completes the decompression and relocation work required by the ROM image. These three files generally do not require direct modification by the user. 5.2.6 System Library File syslib.c This file contains library functions related to the specific target system. These functions provide board-level interfaces for the operating system and applications, making these programs independent of the hardware system. This file contains at least the following functions: sysModel, sysBspRev, sysHwInit, sysHwInit2, and sysMemTop, etc. Among them, sysHwInit is the core of this file, and most hardware initialization work is completed in this part. This system can also optionally add the initialization entry program for hardware devices such as serial ports and network ports to this function. The drivers for related devices can be included as subfiles in syslib.c. 5.3 Creating VxWorks Images Depending on specific needs, various images can be created using makefiles in the command-line environment, or various types of BootROMs can be created by selecting Build Boot Rom in the Build menu of the Tornado integrated environment. 6. Conclusion This paper introduces a novel high-performance embedded processor and provides a detailed explanation of the hardware design and software development process for a network server built around this processor. Given the commonalities in embedded system design across different processors, this paper can serve as a reference for the development of other types of embedded systems.