1. Introduction Currently, railway crossings are basically of three types: manned, monitored, and unmanned. For a long time, the railway department has invested significant manpower and resources in manned and monitored crossings, implementing safety measures. In particular, the technical equipment for manned crossings, with automatic alarm signals as the main facility, is largely complete, creating favorable conditions for the crossing's own safety management. However, automatic alarm devices only consider strengthening the crossing's own supervision and preventing accidents, without addressing how to prevent collisions when abnormal situations occur at the crossing involving moving trains. To further control crossing safety, a DSP-based railway crossing image monitoring system was designed, enabling the driver to receive the system's final assessment of the crossing via GSM-R at an appropriate distance before the train passes. This is of great significance for ensuring the safety of trains and vehicles and pedestrians crossing the crossing. 2 System Overall Framework 2.1 Basic System Components The system mainly consists of industrial cameras, a data buffer, a DSP processor, a CPLD chip, a level crossing transmitting device, and a locomotive receiving device, as shown in Figure 1. Two industrial cameras are installed at both ends of the level crossing to record the movement of pedestrians and vehicles. The data buffer temporarily buffers the image data captured by the cameras after conversion via a USB interface circuit, for later use by the image processing unit. The CPLD chip and DSP processor are the core of the entire hardware system, mainly responsible for real-time processing and analysis of the railway level crossing data to determine if there is a fault at the level crossing. A portable hard drive is used to store photos taken when a level crossing fault occurs. 2.2 System Operation The system's working principle: When the train approaches the level crossing at 1500-2000m, the cameras installed on both sides of the level crossing begin to capture real-time images of the area around the level crossing. The captured video images are sampled by an A/D converter to obtain dynamic sequence image frames, which are then sent to the data buffer. Under the control and assistance of the CPLD, the data in the data buffer is read into the DSP. According to the algorithm designed by the system, the level crossing image data is processed to determine whether there is a fault at the level crossing. If a level crossing malfunctions, its related images are stored on a portable hard drive. Simultaneously, the system analysis results are transmitted in code via the railway wireless communication system GSM-R to a specific receiving device on the train locomotive. The locomotive driver, based on the received signal code, understands the situation at the level crossing ahead and takes appropriate emergency measures, thus preventing level crossing accidents. 3 System Design Scheme 3.1 System Core Components The TMS320C6202, manufactured by TI (Texas Instruments), is the core processor for this module. It is a fixed-point digital processor with a maximum clock frequency of 250MHz and a maximum processing capacity of 2000MIPS. It features an 8-stage pipeline, executing 8 32-bit instructions per instruction cycle. It has 4 main DMA channels and one auxiliary DMA channel, allowing external connection of various devices, including SBSRAM, SDRAM, ASRAM, FLASH, and FIFO, through a 32-bit EMIF interface. The EPM7128SQC100 internally includes a logic array block (LAB), macrocells, extended product terms (shared and parallel), a programmable interconnect array (PIA), and an I/O control block. It provides a low-power operating mode, allowing user-defined signal paths or the entire device to operate in a low-power state. The FN74V245 is a synchronous high-speed buffer device manufactured by TI (Texas Instruments). It features high speed, low-power CMOS, and clock-driven synchronization. As a synchronous device, it means that each end (read/write) of the FIFO uses an independent clock drive signal. These clock signals can be asynchronous or cooperative. The Y7C 1339-166AC is manufactured by Cypress Semiconductor as an extended RAM for DSPs. Its data transfer frequency can reach up to 166MHz, and its storage space is 128k×32a. 3.2 System Hardware Design The image data volume is large, and the algorithm complexity is high. A design scheme for a railway crossing image monitoring system based on DSP is proposed. Simultaneously, the strong flexibility of Field Programmable Gate Arrays (FPGAs) or Complex Programmable Logic Devices (CPLDs) is utilized to complete the system's timing logic control. According to the signal flow, the hardware design of this system can be roughly divided into six modules: image capture, timing control, DSP image processing and external image storage, transmitted signal codes, and locomotive received signal codes. The system hardware structure is shown in Figure 2. The DSP used is a TMS320C6202, the CPLD is an EPM7512BQC208-5, and the data transmission module uses a Siemens MC55 chip. Considering that current domestic and international industrial cameras can directly output digital images and have USB interfaces, they are directly connected to the FIFO via the USB interface circuit. The system uses a CY7C1339B as the system's data memory to store digital video signals and an SS39VF400A as the system's program memory; the DSP is connected to these two memories via its external interface EMIF. The SN74V245, as a high-speed buffer, effectively addresses the significant difference between the video acquisition speed and the DSP's image processing speed. Its front end connects to the camera's USB interface, and the acquired video data is written to the buffer under the drive of a synchronous clock; its back end connects to the 32-bit XBUS of the main processor DSP. The PEPM7512BQC208-5 chip is responsible for coordination between DSPs, control of complex peripherals, and some communication tasks. Its external interfaces connect to the SN74V245, TMS320C6202, SS39VF400A, and a portable hard drive. The system software design adopts a modular approach, dividing the software into several relatively independent functional modules and assigning appropriate input and output parameters to each module, making the interconnection and combination of modules flexible and convenient. The system software mainly consists of an image acquisition module, an image processing module, a data transmission module, and a locomotive receiving module. This system is a DSP-based real-time image processing system. The DSP's main program runs throughout the entire system, including the transfer and processing of acquired images, and interfaces with external SDRAM and FLASH memory, a portable hard drive, and level crossing transmission equipment. For ease of implementation, the main framework is implemented in C language. In the specific algorithm implementation, some key code is implemented using embedded assembly language, and corresponding software optimizations are performed to improve program efficiency. After the C6202 completes power-on startup or reset, the DSP program loads and starts, completing system initialization and setting various parameters, i.e., system boots up, and then waits for external interrupts. When the external interrupt INT1 for image acquisition is triggered, the DSP starts the camera's internal acquisition chip, and the image acquisition module begins to run. When the FIFO is half full, an INT3 interrupt is generated, and the DSP begins to transfer image data through the written interrupt service subroutine. After acquiring an image, an INT2 interrupt is generated, and the DSP begins image processing through the written interrupt service subroutine. After image processing is completed, the processing result needs to be sent to the level crossing transmission device interface through the McBSP interface, and the level crossing fault image is also sent to the external hard drive through the EDMA interface. The DSP's main program flowchart is shown in Figure 3. 5 Conclusion The DSP-based railway level crossing image monitoring system is the result of combining digital image processing technology and wireless network communication technology. It truly realizes the automation and informatization of railway level crossing safety management. Its design scheme abandons the traditional camera-monitor model in image monitoring systems, and uses hardware chips (such as DSP, CPLD) to complete all the computer's processing and control of digital images. It can promptly relay level crossing information to oncoming trains, effectively mitigating potential safety hazards at level crossings and ensuring safe train operation at railway crossings.