I. Component Layout
The layout should refer to the principle block diagram and arrange the main components according to the main signal flow pattern of the single board.
The arrangement of components should facilitate debugging and maintenance; that is, large components should not be placed around small components, and there should be enough space around components that need to be debugged.
For circuit sections with the same structure, adopt a "symmetrical" standard layout as much as possible, and optimize the layout according to the standards of uniform distribution, balanced center of gravity, and aesthetically pleasing layout.
Components of the same type should be placed in the same direction in the X or Y direction. Polarized discrete components of the same type should also be aligned in the X or Y direction to facilitate production and inspection.
Heat-generating components should generally be evenly distributed to facilitate heat dissipation of the single board and the whole machine. Temperature-sensitive devices other than temperature detection elements should be kept away from components that generate a lot of heat.
The layout should meet the following requirements as much as possible: the overall wiring should be as short as possible, and the critical signal lines should be the shortest; high-voltage, high-current signals should be completely separated from low-current, low-voltage weak signals; analog signals should be separated from digital signals; high-frequency signals should be separated from low-frequency signals; and high-frequency components should be sufficiently spaced.
The decoupling capacitor should be placed as close as possible to the power supply pin of the IC, and the loop between it and the power supply and ground should be minimized.
When laying out components, devices that use the same power supply should be placed together as much as possible to facilitate future power supply separation.
II. Electronic Component Routing Methods
1) Clock wiring:
Clock lines are one of the most significant factors affecting EMC. Minimize vias on clock lines, avoid running them alongside other signal lines, and keep them away from general signal lines to prevent interference. Also, keep them away from power supply sections on the board to prevent power and clock interference.
If there is a dedicated clock chip on the board, no traces should be run underneath it; instead, copper should be laid underneath it. If necessary, a dedicated ground plane can be cut for it. For crystal oscillators that many chips reference, traces should also not be run underneath these crystals; instead, copper should be laid for isolation.
2) Right-angle routing:
Right-angle traces are generally considered to be avoided as much as possible in PCB routing and have almost become one of the standards for measuring the quality of routing. So how much of an impact do right-angle traces actually have on signal transmission?
In principle, right-angle routing causes changes in the line width of the transmission line, resulting in impedance discontinuities. In fact, not only right-angle routing, but also obtuse and acute-angle routing can cause impedance changes.
The impact of right-angle traces on signals is mainly reflected in three aspects:
A corner can be considered as a capacitive load on a transmission line, slowing down the rise time; impedance discontinuities can cause signal reflections; and right-angled points can generate EMI.
3) Differential routing:
Differential signals are increasingly used in high-speed circuit design, and the most critical signals in a circuit often require differential structure design.
Definition: Simply put, the driver sends two equal but opposite signals, and the receiver determines the logic state "0" or "1" by comparing the difference between these two voltages. The pair of traces carrying the differential signals is called differential traces.
Compared to ordinary single-ended signal traces, the most obvious advantages of differential signal traces are reflected in the following three aspects:
It has strong anti-interference capability because the coupling between the two differential lines is very good. When there is external noise interference, it is coupled to the two lines almost simultaneously. The receiver is only concerned with the difference between the two signals, so the external common-mode noise can be completely canceled.
It can effectively suppress EMI. Similarly, since the polarities of the two signals are opposite, their electromagnetic fields radiated to the outside can cancel each other out. The tighter the coupling, the less electromagnetic energy is leaked to the outside.
The timing is precise. Since the switching change of the differential signal is located at the intersection of the two signals, unlike ordinary single-ended signals which rely on two threshold voltages (high and low), it is less affected by process and temperature, which can reduce timing errors. It is also more suitable for circuits with low amplitude signals.
The currently popular LVDS (low voltage differential signaling) refers to this small-amplitude differential signaling technology.
For PCB engineers, the biggest concern is how to ensure that the advantages of differential routing can be fully utilized in actual routing. Anyone who has worked with layout will know the general requirements for differential routing, which are "equal length and equal spacing".
Equal lengths are used to ensure that the two differential signals always maintain opposite polarities, reducing common-mode components; equal spacing is mainly used to ensure that the differential impedances are consistent, reducing reflections. The "closest possible principle" is sometimes also one of the requirements for differential traces.
4) Serpentine lines:
Snake-shaped routing is a commonly used routing method in layout. Its main purpose is to adjust delays to meet system timing requirements.
Designers must first understand that serpentine cables can damage signal quality and alter transmission delay, and should be avoided as much as possible when wiring.
However, in actual design, in order to ensure that the signal has enough holding time or to reduce the time offset between signals in the same group, it is often necessary to deliberately make the wires wrapped.
Points to note:
Differential signal lines that appear in pairs are generally routed in parallel, with as few vias as possible. If vias are necessary, both lines should be viad together to achieve impedance matching.
A group of buses with the same properties should be routed side by side as much as possible, and their lengths should be as equal as possible. Vias leading from surface mount pads should be kept as far away from the pads as possible.
