Abstract: This paper introduces a real-time detection method for backlash in mechanical transmission and its specific implementation circuit. The circuit is compact, and the method is reasonable and practical. Practical use has proven its stable performance, fully meeting the needs of practical application and research. Keywords: Mechanical transmission, incremental encoder, synchro servo system. In the mechanical transmission part of a system, regardless of whether the transmission form is gear, chain, cable, or lever, backlash always exists during transmission. Backlash nonlinearity not only increases the system's steady-state error but also affects the system's dynamic quality, lengthening the transition time under a unit step signal, increasing the number of oscillations, and even generating undamped self-oscillations. Therefore, studying the impact of backlash on the system has great practical significance. To study the impact of backlash, it is necessary to obtain the backlash in the transmission. This paper was developed in the research of the control algorithm for a certain type of tank turret. 1. Method for Obtaining Backlash The system block diagram is shown in Figure 1. The backlash is generated by the mechanical transmission device. The position signal fed back from the motor shaft does not contain backlash, while the position signal fed back from the load shaft contains a backlash component. The speed ratio between the motor shaft and the load shaft is fixed, so we can obtain the gap using the following method: multiply the motor shaft position by the "electronic speed ratio" corresponding to the speed ratio of the two shafts to obtain the ideal gap-free position of the load shaft, and then subtract it from the actual position fed back by the load shaft to get the gap at the corresponding moment. 2. Circuit Composition Any computer model can be selected; for research convenience, a 486PC compatible system machine is used. The interface circuit mainly includes a code disk signal shaping, direction determination, and counting buffer section for detecting the motor shaft position; a synchro signal receiving and conversion module for detecting the load shaft position; command output (D/A); and switch I/O. 2.1 Motor Shaft Position Detection Circuit An incremental code disk coaxial with the motor shaft is used as the sensor for detecting the motor shaft position. Incremental code disks are small, highly accurate, and easy to install. For example, a code disk produced in Switzerland has an external dimension of Φ44mm and a thickness of only 22mm, while achieving a maximum accuracy of 9000 pulses/revolution. This system uses a motor-matching code disk produced by FANUC, with a speed of 2000 pulses/revolution. The load shaft position detection uses a synchro, and a fairly high accuracy can be achieved by employing a combination of coarse and fine techniques. The system achieves a maximum resolution of 19 bits, but only 16 bits are actually used. The circuit block diagram related to motor shaft position detection is shown in Figure 2. The encoder counter is composed of cascaded 74LS193 binary reversible counters. The 193 has up/down counting control terminals, a clear terminal, and a preset control terminal, perfectly meeting the circuit requirements. The A, B, and Z three-phase signals generated by the incremental encoder are converted into three sets of differential signals by a long-line drive and sent to the long-line receiving circuit. The A and B pulse signals are 90 degrees out of phase and are used for direction determination and counting; the Z pulse signal is given once per revolution of the motor shaft for clearing (not used for gap measurement, but used in conjunction with the clearing circuit for servo system zeroing). The long-line receiver here is an AM26ls32. The direction determination circuit is shown in Figure 3. The specific direction determination process is shown in Figure 4. As shown in Figure 4, the pulses output by the code disk are decomposed into two pulses, cp+ and cp-, by the direction discrimination circuit. For forward rotation, cp+ is a high-level pulse and cp- is a high-level pulse; for reverse rotation, the opposite is true. A 74LS374 is used for data latching, and a 245 is used for buffering. Since the pulses from the code disk are generated continuously, to avoid the CPU reading the data during counting, CP+ and CP- need to be introduced into the latching circuit, as shown in Figure 5. Here, we use the leading edge of the cp+ and cp- pulses to latch the data, while counting uses the trailing edge of cp+ and cp-, so the latched data is reliable. Simultaneously, the CPU reads the latched data, thus solving the synchronization problem. It should be noted that introducing the read signal into the AND gate that generates the latch signal may cause an error of one code in the A/D conversion. This generally meets the design accuracy requirements of the A/D converter. 2.2 Load Shaft Position Detection Circuit The block diagram of the load shaft position detection circuit is shown in Figure 6. Synchro 1 and synchro 2 are respectively installed on the load shaft and the drive shaft connected to it, forming a coarse and fine combined detection circuit. The SDC module uses the British-made SDC1704. The SDC1704 is an analog continuously tracking synchro/resolver digital converter widely used in military and industrial fields. It features: • Selectable reference voltage frequency: 60Hz, 400Hz, 2.6kHz; • Low thickness (0.4 inches); • 360° full-angle conversion corresponding to 14-bit digital output; • High tracking speed (75 rpm); • Actual voltage varies with external resistance; • DC voltage output proportional to angular velocity; • Lightweight (30 ounces). Depending on the selection, its input signals can be 3 synchro signals + reference signal or 4 resolver signals + reference signal. The output signal is a parallel automatic binary code compatible with TTL levels. The connection between the SDC1704 module and the synchro consists of 5 wires (shown in Figure 7). The signals on the three phase voltage lines are 120° out of phase, and the line voltages between the lines directly determine the values ​​of the three resistors R1, R2, and R3. The magnitude of the reference voltage determines the resistance value of resistor Rf. The principle for selecting resistors is: for R1, R2, and R3, for every 1V increase in signal voltage from the specified rated value, 1.11kkΩ should be connected in series; for Rf, for every 1V increase in reference voltage from the rated value, 2.2kΩ should be connected in series. For example, if the rated line voltage is 11.8V and the rated reference voltage is 26.0V, and a 60V line voltage and 115V reference voltage are desired, the resistor calculation process is as follows: R1, R2, R3: 60 - 11.8 = 48.2V 48.2 × 1.11 = 53.5kΩ Rf: 115 - 26.0 = 89V 89 × 2.2 = 195.8kΩ It should be noted that for R1, R2, and R3, the proportional error between resistors is more important than the simple resistance value. A 1% proportional error will result in an inaccuracy of 17 arcminutes! The interface between the SDC1704 module and the computer is very simple (shown in Figure 7). Two 244 chips are sufficient for the data buffer, and their data output controls are connected together and selected by a single address. To prevent the CPU from reading data during module conversion, the INHIBT pin is controlled using the logic shown in the figure. Since this pin is low to disable conversion, data should be sent to the corresponding I/O port before reading to ensure that the Q of the D flip-flop is 0. The coarse and fine 14-bit data read back from the two SDC1704 modules need to be combined according to their turns ratio to form the angle corresponding to the load axis. During the combination process, gross errors must be considered and error correction handled. Specific details are not elaborated here, but a practical empirical formula is given: 3. Regarding the 16-bit data strobe signal I/OCS16 in the circuit: If using a PC or PC-compatible machine, the 16-bit data input/output must provide the I/OCS16 signal. This signal is generally given in textbooks as shown in Figure 8. In actual use, this method has been found to be unreliable and prone to causing crashes or misoperations. The main reason is that circuits constructed in this way are prone to mutual interference. If circuit 1 needs to perform a 16-bit read or write operation, its corresponding port address 1 is 0, and the corresponding I/OCS16 signal should be low (0) during the read or write process. However, circuit 2 has no I/O request at this time (it certainly won't), but because circuit 1's read or write operation opens the corresponding tri-state gate in circuit 2, circuit 2 forces the I/OCS16 signal high. If the gate circuit's load capacity is slightly insufficient, the I/OCS16 signal will inevitably be neither high nor low as it should be. Replacing it with the circuit shown in Figure 9 eliminates this problem. 4. Correct Circuit Usage When developing the application program, it's important to ensure that the 0th bit of the encoder disk matches the 0th bit of the synchro at the beginning. Our method is to send a command to start the system, acquire the load axis position, and when it reaches 0, set the 193 pin to 0 via the preset terminal. This circuit structure is reasonable and practical, and has been successfully applied to gap-related project research. Practical use has proven its reliability and good performance.