As we all know, high-quality substrates and high-quality epitaxial wafers for silicon carbide MOSFETs (SiC MOSFETs) can be purchased from external sources. However, this only provides a good foundation for obtaining a silicon carbide device. High-performance silicon carbide devices have extremely high requirements for device design and manufacturing processes. Next, let's take a look at the progress and achievements that Onsemi has made in the design and manufacturing of SiC MOSFET devices.
Die Layout
The surface of a chip is generally as shown in Figure 2, consisting of source pads, gate pads, and Kelvin source pads. Some chips only have gate pads, such as the chip in the image above, which lacks Kelvin source pads.
Figure 2
Here we observe a narrow ring around the chip, sometimes called a voltage withstand ring, which is quite descriptive. Its main function is to improve the chip's voltage withstand capability. We call it a voltage withstand ring (Edge Termination Ring), typically found in a JTE structure. A chip mainly consists of three parts: a Terminal Ring, a Gate Pad, a Kelvin Source Pad, and active cells. The outer ring of the chip is the voltage withstand ring, the Gate Pad transmits the gate signal to each cell, and inside are millions of active cells. Active cells are usually the focus of attention because the chip's switching and conduction performance is largely related to them. Here we summarize the chip layout and the characteristics of each part to help you better understand the chip.
Edge termination ring
• The switching units surrounding the chip currently mostly adopt a JTE structure.
• Effectively controls leakage current, improving the reliability and stability of SiC devices;
• It reduces the electric field concentration effect and improves the breakdown voltage of SiC devices. The breakdown voltage of SiC MOSFETs is related to each specific switching unit and is also greatly related to the withstand voltage ring.
• To prevent ion migration, JTE (Joint Transfer Therapy) technology can be used to suppress the drift of mobile ions, thereby improving the reliability and stability of SiC MOSFETs. Specifically, JTE technology can form deeply doped control regions at the edge of the SiC MOSFET, which can effectively suppress the drift of mobile ions. Furthermore, JTE technology can introduce special substances, such as nitrogen and boron, into the control regions. These substances can chemically react with mobile ions, thereby reducing their accumulation and drift within the MOSFET.
Gate pad and Kelvin source pad.
The main function of the gate pad is to transmit the gate signal to each switching unit. It is also worth mentioning that ON Semiconductor's chips integrate the gate resistor, which can save space and some cost in module packaging.
The primary advantage of Kelvin sources is increased switching speed and reduced switching losses. However, special design is required when using them in parallel.
Active Cell
• The path for current to turn on and off
• All switching units are connected in parallel.
• With fixed cell characteristics, the number of cells determines the on-resistance and short-circuit current capability of the entire chip.
Currently, it is mainly divided into two types of structures: planar and trench.
We have already gained an understanding of the surface layout of SiC MOSFETs. In SiC chips, the edge terminal and active cell are two crucial components. ON Semiconductor has extensive experience in JTE design, having evolved from M1 to M3 in SiC MOSFETs. Through several generations of technological iteration, JTE design simulation and manufacturing are highly mature. Let's summarize some characteristics of JTE and some design considerations.
SiC JTE (junction extension region) is a structure used to improve the voltage blocking capability of silicon carbide (SiC) power devices. The design of SiC JTE is crucial for achieving the required breakdown voltage and avoiding premature breakdown due to high electric fields at the device edges.
Here are some key considerations for SiC JTE design:
1. Width and doping of the JTE region: The width and doping concentration of the JTE region determine the electric field distribution at the edge of the device. A wider and heavily doped JTE region can reduce the electric field and increase the breakdown voltage.
2. Taper angle and depth of the JTE: The taper angle and depth of the JTE affect the electric field distribution and breakdown voltage. A smaller taper angle and a deeper JTE can reduce the electric field and increase the breakdown voltage.
4. Surface passivation: The surface passivation layer is crucial for reducing surface leakage and improving breakdown voltage. The passivation layer needs to be carefully designed and optimized specifically for SiC JTE devices.
5. Thermal Design: SiC JTE devices can operate at higher temperatures than their Si counterparts. However, high temperatures can also degrade device performance and reliability. Therefore, thermal design considerations, such as heat dissipation and thermal stress, should be taken into account during the SiC JTE design process.
Overall, SiC JTE design is a complex process involving trade-offs between various design parameters. Careful optimization and simulation are required to achieve the desired device performance and reliability.
Active Cell Switching Unit – The Core of SiC MOSFET
The switching unit is a crucial component of a SiC MOSFET. We can categorize MOSFETs (silicon and silicon carbide) into two types based on their gate structure: planar and trench structures. Their schematic diagrams are shown in Figure 3. Structurally, silicon and silicon carbide MOSFETs are the same, but their manufacturing processes and designs differ significantly due to the unique properties of silicon and carbide materials. For example, SiC extensively utilizes dry etching and high-temperature ion implantation processes, employing different implanted elements.
Figure 3
Currently, the vast majority of SiC MOSFETs internationally adopt the planar structure shown in Figure 3A, while a small number of manufacturers use the trench structure shown in Figure 3B. From a developmental perspective, they will eventually evolve into trench structures. However, the potential of the current planar structure can still be further explored, and the trench structure has not yet demonstrated its full potential. Here, we introduce a unified metric to measure their performance – Rsp (Rdson * area), which indicates the on-resistance per unit area. Planar SiC MOSFETs have the advantages of high reliability and simple design and fabrication. ON Semiconductor's SiC MOSFETs used in automotive main drive inverters have reduced their Rsp from 4.2 mΩ*cm² in the first-generation M1 to 2.6 mΩ*cm² in the M2. The latest M3e has an Rsp performance at room temperature that is consistent with that of competitors' trench-structured SiC MOSFETs, while its Rsp at high temperatures is lower than that of competitors' trench-structured SiC MOSFETs, achieving an industry-leading level. The cell pitch value of the M3e is comparable to that of current trench-structured SiC MOSFETs, indicating that ON Semiconductor has achieved a considerably high level of optimization in planar SiC MOSFET development. Of course, MOSFET performance depends not only on Rsp (reverse polarization), but also on switching losses. Through the development of previous generations of SiC MOSFETs and based on extensive customer application feedback, ON Semiconductor has optimized conduction losses, turn-on losses, reverse recovery losses, and short-circuit time in its SiC MOSFET devices, enabling them to achieve optimal efficiency in customer applications.
The design and manufacturing direction of active cells in the planar structure of SiC MOSFETs is mainly to reduce the pitch value, increase the density of switching cells, reduce Rdson, and improve the reliability of the gate oxide layer.
As shown in Figure 3A, in order to minimize the on-resistance, the spacing of the switching units needs to be adjusted. The pitch value and Wg, which is the width of the gate, are related. When the pitch value decreases, Wg also decreases accordingly. This is beneficial to the reliability of the gate. In SiC MOSFETs, the gate oxide layer is very thin, less than 100 nanometers. Therefore, dry etching is used in the SiC manufacturing process to control the processing precision.
Based on the on-resistance diagram in Figure 3A, we can derive Rdson = Rs + Rch + Ra + Rjfet + Rdrif + Rsub. Here, Rch and Ra account for the largest proportion, exceeding 60%, making them a key focus for design and process optimization. However, simply reducing the gate width of the switching unit doesn't necessarily reduce Rsp. Reducing the gate width (Wg) beyond a certain range can actually increase Rsp. During design, the interrelationships of these parameters need to be comprehensively considered to achieve a more ideal optimization result. ON Semiconductor, through several generations of process iterations, has achieved relatively mature performance, yield, and reliability in its planar SiC MOSFETs.
In the chip, each active cell is connected in parallel.
Here are some key considerations for SiC MOSFET Rdson design:
1. Channel width and doping: The channel width and doping concentration of a SiC MOSFET affect Rdson and current density. Wider and heavily doped channels can reduce Rdson and increase current carrying capacity.
2. Gate oxide thickness: The thickness of the gate oxide layer affects the gate capacitance, which in turn affects the switching speed and Rdson. A thinner gate oxide layer can improve the switching speed, but it may also increase the gate leakage current and the risk of oxide layer breakdown failure.
3. Gate Design: Gate design affects gate resistance, which in turn affects switching speed and Rdson. Lower gate resistance can improve switching speed, but may also increase gate capacitance. Overall, SiC MOSFET Rdson design is a complex process involving comprehensive consideration of the interactions between various parameters. Careful optimization and simulation, as well as experimentation and testing, are required to achieve the desired device performance and reliability.
Integrated on-chip gate resistor
All On Semiconductor SiC MOSFETs developed for main drive inverters integrate the gate resistor. Figure 5 shows the difference between having and not having a gate resistor. Figure 5A shows MOSFETs that do not require a gate resistor (it is integrated on the chip), while Figure 5B shows MOSFETs that require an additional gate resistor.
Figure 5
Integrated gate resistors offer several advantages for module design and manufacturing:
• It simplifies the process of module bonding lines and reduces the failure rate.
• Reduced welding resistance in the DBC process
• Reduced BOM and manufacturing costs
• Relatively miniaturized design and manufacturing facilitate packaging
Due to space limitations and the highly complex design and manufacturing process of SiC MOSFETs, it cannot be explained clearly in a few words. Hopefully, this article will provide a basic understanding of SiC MOSFET design and manufacturing. ON Semiconductor has over ten years of experience in the design and manufacturing of SiC power devices. Our SiC MOSFET products have undergone several generations of iteration, and their performance, quality, and reliability have become stable and competitive. We warmly welcome you to choose and use our SiC MOSFET products.
