Flip-chip technology refers to the process of depositing bumps (including solder balls, lead-free solder balls, copper-copper bumps, and gold bumps) directly on the I/O pads of a chip, or depositing bumps after RDL wiring. The chip is then flipped and heated, causing the molten solder to bond with the substrate or frame, thus fanning out the chip's I/O to form the desired package. A schematic diagram of a flip-chip package product is shown in the figure.
Flip-chip technology was first developed by IBM in the 1960s and mass-produced in the late 1990s, primarily used in high-end products (such as CPUs and GPUs). With the emergence of copper pillar bump technology, combined with the rapid development of consumer smart electronics (such as mobile phones and wearable products) and the demands for product performance, more and more products are shifting from traditional wire bonding packaging to flip-chip packaging.
Compared with traditional wire bonding technology, flip chip packaging technology has the following advantages.
(1) High VO density.
(2) Due to the use of the bump structure, the interconnect length is greatly shortened, the interconnect resistance and inductance are smaller, and the electrical performance of the package is greatly improved.
(3) The heat generated in the chip can be directly transferred to the packaging substrate through the solder bumps, so the chip temperature will be reduced.
Flip chip manufacturing encompasses many different process methods. Currently, the main bump technologies used in the industry for flip chips include gold bumps, tin bumps, and copper pillar bumps, with corresponding soldering processes primarily being ultrasonic thermoforming, reflow soldering, and thermoforming. Due to technological advancements and product variations, underfill processes are mainly categorized into capillary underfill, molding compound underfill, and non-conductive adhesive (NCP) or non-conductive film (NCF) underfill. The figure shows a schematic diagram of the bump process.
As wafer CMOS processes continue to advance towards higher densities such as 16nm, 10nm, and 7nm, the requirements for chip V0 density and performance are becoming increasingly stringent. This necessitates the use of flip-chip technology to meet these demands. Flip-chip packaging also places increasingly higher demands on packaging processes and reliability, including high-density micro-bump technology, small-pitch flip-chip bonding technology, and underfill technology. Each process method has its own characteristics and application scope. For example, the choice of circuit board or substrate type—whether organic, ceramic, or flexible—determines the selection of assembly materials (including bump type, flux underfill material, etc.) and, to some extent, the required equipment. Therefore, future flip-chip packaging requires a comprehensive approach that considers product application, chip design, packaging design, packaging materials, packaging equipment, and packaging processes to select the optimal packaging solution.
Today, flip-chip technology is widely used in the consumer electronics field, and its applications in the Internet of Things, automotive electronics, big data and other fields will be even more extensive in the future. Flip-chip packaging is considered an essential process for advancing the manufacturing of low-cost, high-density portable electronic devices.
