System-in-Package (SiP) refers to the integration of one or more chips and various components into a single package or module through system design and specific packaging processes, thereby achieving complete circuit integration, as shown in Figure 7-115. Unlike System-on-Chip (SoC), which is often used to integrate digital and logic circuits, SiP is more suitable for applications of analog circuits such as microwave, radio frequency, and power circuits where functional integration cannot (or is very difficult) be achieved on a single chip.
As a primary technology and method for designing, developing, and packaging integrated circuit products, SiP (System-in-Package) does not have a fixed packaging form or process; it can be implemented on most existing packaging types. Typically, SiP uses the relatively flexible LGA design due to the diverse functionalities of its products, as shown in the figure. However, with the rapid adoption of this technology in larger and more complex system circuits, BGA (Blocked GA) and integrated modules, which provide more I/O ports, are also becoming increasingly widely used. Furthermore, SiP packaged modules often require electromagnetic shielding to eliminate the interaction between the module circuitry and the environment, which can usually be achieved using a simple metal cover. Currently, high-performance, high-reliability SiP modules are increasingly using a process of encapsulating with plastic and applying a metal coating to achieve electromagnetic shielding.
The types of substrates and carriers used in SiP mainly include: thin film, thick film and low temperature sintered ceramic (LTCC) substrates; high density lead frame substrates; single-layer, multi-layer and embedded organic substrates; fan-out wafer-level substrate-free redistribution (RDL) interconnects, etc.
The main packaging processes and structures of SiP include: multi-chip SMT + WB/FC; chip stack SMT + WB/FC; high-density 3D/2.5D packaging; stacked package (POP); fan-out wafer-level SiP, etc.
A typical SiP process flow is shown in the figure. Because SiP involves a large number of diverse chips and components, new packaging processes are required, such as SMT (Surface Mount Technology) and electromagnetic shielding sputtering coating. Although the main semiconductor packaging processes and equipment can be shared, SP (Surface Mount Technology) processes also have many unique new requirements for these general-purpose packaging processes.
(1) High-density, small-pitch surface mount technology: SiP technology is the biggest driving force for the miniaturization of components and pre-packaged chips (WICSP, ultra-thin and ultra-small CSP). Inductors and capacitors with even smaller sizes (008004) in the 0201 and 01005 zones were first used in large quantities in SiP modules. The I/O pitch of advanced WLCSP is less than 200μm, which is close to the FC process. These ultra-small components must be mounted on the SiP substrate using high-speed, high-precision SMT equipment and processes, and connected by solder paste and solder reflow processes. Solder paste is a uniform mixture of solder particles and flux. The selection of solder alloy composition, particle size distribution and flux type is very important and should usually be determined according to the product type and process flow.
(2) Molding: For ultra-small components and chips, the corresponding high density and ultra-small spacing may cause the molding compound to not be fully filled, thus creating potential reliability issues. Common improvement methods include optimizing molding process parameters, using special designs to increase the flow and filling of molding compound, changing the size and distribution of solid particles in the molding compound, and using the Compresion molding process, which facilitates uniform filling.
(3) Electromagnetic shielding metal coating: As shown in the figure, the electromagnetic shielding metal coating is formed on the surface of the molding compound through plasma sputtering or direct electroplating. Because of its flexible process, strong coating adhesion, ease of production capacity expansion, and lack of wastewater treatment required by wet electrochemical processes, plasma sputtering metal coating has gradually become the mainstream process. The electromagnetic shielding metal coating generally consists of multiple metal layers to ensure a strong bond between the metal coating and the molding compound surface. The main layer metal is often pure copper, utilizing its excellent conductivity to achieve electromagnetic interference shielding; the outer layer metal can be stainless steel, ensuring the package has wear resistance and good oxidation resistance. To form complete electromagnetic shielding, the metal coating must cover the top surface and all four sides and be grounded. For higher and more complex system-level packages, partitioned electromagnetic shielding is also used to further improve the overall electromagnetic shielding effect of the system.
