Setup time and hold time are among the most important concepts in time series analysis, and a deep understanding of setup time and hold time is the foundation for conducting time series analysis.
Before discussing setup and hold times, we'll start with CMOS circuits.
1. Introduction to CMOS Transistors
Metal-oxide-semiconductor (MOS) transistors are classified as either P-type or N-type transistors. Integrated circuits constructed using MOS transistors are called MOS integrated circuits, while complementary MOS integrated circuits, composed of both PMOS and NMOS transistors, are called CMOS-ICs (Complementary MOS Integrated Circuits).
A MOSFET is essentially a switch, as shown in the diagram below.
Therefore, an NMOS requires a high input voltage (logic 1) to conduct, while a PMOS requires a low input voltage (logic 0) to conduct. You can think of an NMOS as a "positive switch" and a PMOS as a "negative switch".
The current process mainly uses CMOS technology, which combines PMOS and NMOS transistors into a single unit called a CMOS cell or inverter cell.
Therefore, many articles analyze CMOS inverters because CMOS inverters are the basic unit of CMOS circuits, or can be regarded as the smallest unit.
Therefore, we start with CMOS inverters.
1.1 CMOS Inverter
An inverter is designed so that if the input bit is 1, the output bit is 0; and if the input is 0, the output bit is 1. However, real-world inverters are not quite this ideal.
The CMOS inverter circuit is as follows:
When vI=0V on the left, vGND=0V, VTN is cut off, |vGSP|=VDD, VTP is turned on, vO≈VDD, and the gate circuit outputs a high level. During this process, the power supply loop from VDD to ground GND is not turned on, so theoretically there is no current flowing from VDD to GND, and therefore the power consumption is 0.
When vI=VDD on the left, VGND=VDD, VTN is on, NMOS is on, |VGSP|=0V, VTP is off, PMOS is off, vO≈0V, and the gate output is low. However, the power supply loop from VDD to ground GND is not on, so theoretically there is no current flowing from VDD to GND, and therefore the power consumption is 0.
If 0V is defined as logic 0 and VDD is defined as logic 1, the logic "NOT" function will be implemented.
Therefore, theoretically, CMOS consumes no power during data transmission, but in reality, it's impossible to have absolutely no power consumption, although it will be very low. So, given how crucial low power consumption is today, it's no surprise that CMOS has become the mainstream technology.
2. CMOS logic circuits
2.1 CMOS Gate Circuits
A CMOS inverter is a NOT gate, and NOT gates can be combined to form NAND gates and OR gates.
CMOS NAND gate
The CMOS NAND gate circuit and its behavior are shown in the following figure:
When a = 0 and b = 0, the PMOS connected in parallel above is turned on, and the NMOS connected in series below is turned off, resulting in an output X = Vdd = 1.
When a = 0 and b = 1, the PMOS connected in parallel above is turned on, and the NMOS connected in series below is turned off, resulting in an output X = Vdd = 1.
When a = 1 and b = 0, the PMOS connected in parallel above is turned on, and the NMOS connected in series below is turned off, resulting in an output X = Vdd = 1.
When a = 1 and b = 1, the PMOS connected in parallel above is cut off, and the NMOS connected in series below is cut off, resulting in an output X = Vdd = 0.
As can be seen, this circuit implements the NAND function.
CMOS NOR gate
The CMOS NOR gate circuit and its behavior are shown in the following figure:
When a = 0 and b = 0, the PMOS connected in series at the top is turned on, while the NMOS connected in parallel at the bottom is turned off, and the output X = Vdd = 1;
When a = 0 and b = 1, the PMOS connected in series at the top is cut off, and the NMOS connected in parallel at the bottom is turned on, resulting in an output X = Vdd = 0.
When a = 1 and b = 0, the PMOS connected in series at the top is cut off, and the NMOS connected in parallel at the bottom is turned on, resulting in an output X = Vdd = 0.
When a = 1 and b = 1, the PMOS connected in series at the top is cut off, and the NMOS connected in parallel at the bottom is turned on, resulting in an output X = Vdd = 0.
As can be seen, this circuit implements the NOR function.
2.2 Bistable Devices
A bistable device is a device that has two stable states: 0 and 1. Bistable devices are the basic modules of memory devices. One circuit structure of a bistable device is a cross-coupled inverter structure, as shown in the figure below:
Connecting two inverters together creates a bistable device. Why is it bistable? Let's analyze it now:
Since there is no input, we assume that the output of I1 is initially 1, i.e., Q=1; then the input of I2 is 1, and Q' is 0. This feedback to the input of Q causes the output of Q to be 1, thus stabilizing the state of Q at 1. Therefore, this device has a stable state of 1, as shown in the figure below:
Let's assume that the output of I1 is initially 0, i.e., Q = 0; then the input of I2 is 0, and Q' is 1. This feedback to the input of Q causes the output of Q to be 0, thus stabilizing the state of Q at 0. Therefore, this device also has a stable state of 0, as shown in the figure below:
Therefore, this type of cross-coupled inverter is a bistable device. However, it should be noted that the circuit may exist in a third state, namely the metastable state discussed in the previous article.
Why introduce bistable devices? Because latches and registers are bistable devices, and they both have two stable states, 1 and 0. It is precisely because they have two stable states that they can be used to store data. In other words, bistable circuits (such as cross-coupled inverters, latches, and registers) can store data.
Let's take a look at latches and triggers.
2.3 Latch
Obviously, the cross-coupled inverter described above has no input and cannot store the input data. Therefore, a bistable circuit with an input structure similar to a cross-coupled inverter is needed, which is the latch.
Latch: No trigger signal is required; the setting to 0 or 1 operation is completed directly by the input signal.
The most common and basic latch is the SR latch, and the commonly used latch is the D latch. This section will only introduce the RS flip-flop and the D flip-flop.
2.3.1 SR Latch
The SR (Set-Reset) latch, also called a basic RS flip-flop, is a fundamental component in various flip-flops and is the simplest type of flip-flop. The circuit structure and symbol of an SR latch are shown in the following figure:
The SR latch built here using NOR gates can also be built using NAND gates; you just need to replace the NOR gates with NAND gates.
Working principle:
The S terminal is the set terminal; when S=1, the output Q is set to 1.
The R terminal is the reset terminal; when R=1, the output Q is reset to 0.
When S=0 and R=0, the output Q retains the value of the previous state, which means that the original state is latched.
When S=1 and R=1, according to the characteristics of a NAND gate, Q=0. Therefore, Q=Q, which does not conform to the logic of outputting Q'=~Q. Thus, S=1 and R=1 is an unacceptable state. This is also a limitation of the SR latch.
In engineering, to remove this restriction, a signal A is usually connected to the S terminal and simultaneously input to the R terminal through an inverter (NOT gate). In this way, S and R cannot be 1 at the same time.
Although the SR latch circuit is simple, it has two drawbacks in application:
S and R cannot both be 1; this is inconvenient.
The timing of the latch is unclear; at any moment, the input can directly change the output state. In other words, it's unknown when or what data was latched, and there's no reference point to accurately determine the circuit's state.
Next, we will analyze the transmission delay of the SR latch:
Assume the initial state of the SR latch is Q=0, Q'=1, and the propagation delay of the NAND gate is tpd. The input signal waveform is shown in the figure below:
After the falling edge of S arrives, and after the propagation delay time tpd of G1, the Q terminal becomes high.
A high-level signal is applied to the input of gate G2, and after the propagation delay time tpd of gate G2, Q' becomes low.
Once the low level of Q' is fed back to the input of G1, the flip-flop will remain in the q=1 state even if S=0 changes to S=1.
As can be seen, in order to ensure that the flip-flop flips reliably, the signal S=0 can only be canceled after the state Q`=0 is fed back to the input of G1.
Therefore, the width tw of the low-level signal at input S should satisfy tw≥2tpd.
Similarly, if a reset signal is input from the R terminal, its width must be greater than or equal to 2tpd.
As can be seen, if the signal width input to the S and R terminals is very small, such as with glitches, the output will not change. The structure of the SR latch is very useful in glitches during gated clock switching; I will write a separate article to discuss this circuit later.
2.3.2 D Latch
To address the shortcomings of the SR latch, an improved structure was developed: the D latch.
The most distinctive feature of the D latch is the introduction of a special signal—the clock signal.
Note: A clock signal is first and foremost a signal; it's a special signal named so because of its special nature and importance. The same applies to a reset signal. When analyzing clocks, please remember that a clock signal is first and foremost a signal.
The purpose of introducing a clock signal is as a reference and for synchronization. Because a clock is a special signal that cycles through high and low levels, its behavior is deterministic, and the same clock signal is sent to different circuits. Therefore, it can be used as a reference.
For example, after introducing a clock signal, the D latch can only function when the clock is valid, which adds a prerequisite to SR. By comparing with the periodic clock signal, the latching time can be clearly determined.
The common structure and circuit symbol diagram of D latch are shown below:
As can be seen, the D latch can be divided into a front-end gate circuit (two AND gates and one NOT gate) and a rear-end SR latch.
Let's analyze its functions below:
The input is Clk and D, meaning there are four possible inputs:
When clk=0, both red S and red R are 0. That is, the input of the SR latch is 00. According to the function of the SR latch, the outputs Q and Q' will remain in their original state. Therefore, when clk=0, no matter what D is, the outputs Q and Q' will not change with D, but will only be related to their original state, that is, they will remain unchanged.
When clk=1, R=(1·D')=D'; S=(1·D)=D.
In other words, when clk=1, the inputs of the SR latch are complementary, and S and R will not be valid simultaneously. When D=1, S=1, set is valid, and output Q=1; when D=0, R=1, reset is valid, and output Q=0; therefore, we can know that when clk=1, output Q=D, that is, the output equals the input.
Based on the above analysis, the function of the D latch structure is as follows: when clk=1, data flows to Q through the D latch; when clk=0, Q retains its original value. Such a latch is also called a transparent latch or a level-sensitive latch.
Note: Level sensitivity here means that the input can only cause a change in the output when the clock level is 1.
2.4 Flip-Flop
Although latches are simple in structure, small in size, and fast, they are level-sensitive. When the clock is high, any change in the input signal will cause a change in the output at any time, and there may be multiple changes during a single high-level clock cycle. Moreover, they are greatly affected by wiring delays, making it difficult to guarantee that the output is free of glitches.
To overcome this shortcoming, edge-triggered flip-flops were invented. The most significant characteristic of edge-triggered flip-flops is their edge sensitivity, meaning they depend solely on the state of the input signal when the falling (or rising) edge of CLK arrives, regardless of the state of the input signal before or after it. This improves reliability and enhances noise immunity.
The most common and simplest trigger is the D trigger.
2.4.1 D Flip-Flops
The structure and circuit symbol diagram of the D flip-flop are shown below:
A D flip-flop can be composed of two D latches with opposite phases of the driving clock. The first D latch is called the master latch, and the second D latch is called the slave latch. Therefore, a D flip-flop can also be called a master-slave flip-flop.
Next, we will analyze the function of D triggering (note that the clock of the main latch is the inverted clock):
Assume the data to be transmitted is D=D1:
When the clock clk = 0, the master latch opens to transmit data, sending the input to the input of the slave latch, i.e., Qm = D1. Then, when clk changes from 0 to 1, the master latch prepares to close, maintaining its original value D1. At the same time, the slave latch prepares to open, transmitting the value of Qm to the output Qs, i.e., Qs = Qm = D1.
When clk=1, the master latch is closed, Qm remains unchanged at D1, i.e., Qm=D1; the slave latch is open, Qs=Qm=D1. Then, as clk changes from 1 to 0, the master latch prepares to open, ready to transfer data; while the slave latch prepares to close. When clk=0, the master latch opens to transfer data, sending the input to the slave latch's input, i.e., Qm *= D2; simultaneously, the slave latch closes. Since the new Qm, i.e., Qm*, has not yet reached the slave latch's D input, when the slave latch closes, it latches the original value, i.e., D1. Therefore, the output is Qs = D1. Then, on the next rising edge, D2 is transferred...
The analysis above shows that a D flip-flop latches the value sampled at the rising edge of the clock and holds it for one clock cycle. This type of flip-flop that latches data at the rising edge of the clock is called a positive edge flip-flop. There is also a negative edge flip-flop, which will not be discussed here.
There are many other topics that extend from D flip-flops, such as registers:
A register is composed of multiple D flip-flops (one D flip-flop can be regarded as a 1-bit register); a register can be regarded as a multi-bit DFF.
For example, a trigger with an enable function:
For example, a trigger with a reset function:
3. Establishment time and retention time
3.1 Definitions of setup time and retention time
Below, we will analyze D flip-flops to understand setup and hold times.
If we want to understand a concept in depth, then we must know its clear definition.
Setup time and hold time are both terms used to describe the characteristics of a trigger, such as a D trigger:
The timing diagram is as follows:
Setup time (Tsu):
It refers to the time during which the data remains stable before the rising edge of the clock signal arrives at the flip-flop. If the setup time is insufficient, the data will not be stably latched into the flip-flop at the rising edge of the clock. Tsu refers to this minimum setup time.
Hold time (Th):
This refers to the time it takes for the data to remain stable after the rising edge of the clock signal arrives at the flip-flop. If the hold time is insufficient, the data cannot be stably latched into the flip-flop. Th refers to this minimum hold time.
Setup time and hold time are essentially the time windows during which data must remain stable before and after the rising edge of the clock; otherwise, the data cannot be correctly stored in the trigger.
3.2 Why are establishment time and retention time needed?
So why are there requirements for establishment and maintenance times?
The gate circuit of the D flip-flop is as follows:
We know that D flip-flops latch data on the rising edge, that is, when clk latches data from 0 to 1. Let's see what happens on this rising edge:
Suppose the original data is 1 (that is, the data latched from the latch is 1), and the data we want to latch is 0.
For an input of 0 at the D terminal to be output at the Q terminal, the master latch needs to stably lock the input 0. The slave latch is responsible for transmitting the data latched by the master latch. Therefore, we will focus on analyzing the master latch.
To simplify the analysis, assume the delays of inverters, AND gates, and NOR gates are all tpd. We will analyze the input of the SR latch. Assuming the delay of input D from 0 to 1 relative to the rising edge of CLK is tdd, the waveform at input S is as follows:
As can be seen, inverting CLK has a delay of tpd, and the input at the S terminal also has a delay of tpd relative to the D terminal. Thus, the width of the first pulse after S = ~CLK & D is tw = tdd.
The same conclusion can be obtained by analyzing the R-end.
In other words, the time it takes for the input data D to stabilize before the rising edge of the clock is represented by the pulse width of the S/R terminal signal of the SR latch.
Referring to the analysis in 2.3.1, the SR latch has requirements on the pulse width of the input signal.
The width tw of the low-level signal at input S should satisfy tw≥2tpd
Therefore, we can obtain tw = tdd ≥ 2tpd.
In other words, the data must have a settling time of at least 2tpd (where tpd is the gate delay) before the rising edge of the clock arrives in order to be correctly sampled.
This is the setup time: Tsu ≥ 2tpd
Similarly, we can obtain the hold time: Th≥2tpd
Therefore, our conclusion is that due to the delay of the gate circuit and the circuit structure of the flip-flop, the setup time and hold time must exist; otherwise, the functional requirements of the flip-flop cannot be met.
4. Postscript
Setup time and hold time are the most fundamental concepts in timing analysis. Many engineers only know the definitions of these two concepts, but may not understand the real reasons why setup and hold times are needed. This article analyzes the reasons for the need for setup and hold times step by step from the structure and characteristics of CMOS gate circuits, providing assistance for a deeper understanding of these two concepts.
