Abstract : Integrated circuit chips are constantly developing towards higher density, higher performance, and thinner and smaller dimensions to meet IC packaging requirements. Backside thinning of patterned silicon wafers has become an important process in the back-end of semiconductor manufacturing. With the application of large-diameter silicon wafers, the thickness of silicon wafers has increased accordingly, while advanced packaging technologies require thinner chips. Ultra-precision grinding, as the main process for backside thinning of silicon wafers, has been widely used. This paper analyzes several commonly used silicon wafer backside thinning technologies, discusses the processing principle, process characteristics, and key technologies of silicon wafer backside grinding based on the self-rotation grinding method, and introduces the challenges and new progress in silicon wafer backside grinding technology. Keywords: silicon wafer; backside thinning; grinding; IC 1 Introduction In order to increase IC chip production and reduce unit manufacturing costs, the basic material for ICs, silicon wafers, are required to have larger diameters. Currently, 200mm silicon wafers are the mainstream product, and the development is moving towards 300mm silicon wafers. More than a dozen 300mm silicon wafer production lines have been established worldwide, and by 2013, it is expected that 450mm (18-inch) diameter silicon wafers will be used. As silicon wafer diameters increase, the thickness of the prime wafer also increases to ensure sufficient strength during circuit fabrication. The thicknesses of 150mm and 200mm diameter wafers are 625mm and 725mm respectively, while the average thickness of a 300mm diameter wafer reaches 775mm. On the other hand, IC technology is advancing rapidly, moving towards higher speeds, greater integration, higher density, and higher performance. Microelectronic products are developing towards thinner and smaller designs while continuously improving integration, speed, and reliability. Correspondingly, new chip packaging technologies are constantly emerging, requiring increasingly thinner chips. Early dual in-line packages (DIPs) corresponded to chips with a thickness of around 600mm, BGA packages used chips with a thickness of 375mm, and AFCP (Automatic Front-End Packaging Package) chips with a thickness of around 125mm. Some smart cards use chips with a thickness below 100mm, and high-performance electronic products' 3D packaging even requires ultra-thin chips with a thickness of less than 50mm. 2. Backside Thinning Technology of Silicon Wafers The effective thickness of the circuit layer on the silicon wafer is generally 5-10mm. In order to ensure its function, a certain support thickness is necessary. Therefore, the thickness limit of the silicon wafer is 20-30mm. This only accounts for a small part of the total thickness. The substrate material, which accounts for about 90% of the total thickness, is to ensure that the silicon wafer has sufficient strength during manufacturing, testing and transportation. Therefore, after the circuit layer is made, the silicon wafer needs to be backside thinned to achieve the required thickness. The silicon wafer is then diced to form thinned bare chips. The thinned chips have the following advantages: (1) Improved heat diffusion efficiency As semiconductor structures become more and more complex and the integration level becomes higher and higher, the transistor volume continues to shrink. Heat dissipation has gradually become a key factor affecting chip performance and lifespan. Thinner chips are more conducive to heat dissipation. (2) Reduced chip packaging volume Microelectronic products are increasingly developing towards thinner and smaller. Reducing the chip packaging volume is the only way to adapt to this development trend. (3) Improved mechanical properties: The mechanical properties of the chip are significantly improved after thinning. The thinner the silicon wafer, the better its flexibility and the less stress caused by external impact. (4) Improved gas performance: The thinner the wafer, the shorter the connection between components, the lower the on-resistance of the components, and the shorter the signal delay time, thereby achieving higher performance. (5) Reduced dicing workload: Thinning before dicing can reduce the amount of processing during dicing and reduce the incidence of chip chip breakage. In the future, the thinning of the back side of silicon wafers will tend to reach the limit thickness of 20-30mm. When the chip thickness is less than 50mm, it can be bent to a certain extent without breaking. Special ultra-thin chips can even be bent at will and can be used to make flash memory chips and electronic tags, etc. Currently, the main back-side thinning technologies for silicon wafers include grinding, lapping, chemical mechanical polishing (CMP), dry polishing, electrochemical etching, wet etching, plasma-assisted chemical etching (PACE), and atmospheric downstream plasma etching (ADPE). Among these, grinding, CMP, wet etching, ADPE, and dry polishing are the most commonly used back-side thinning technologies. Grinding has high processing efficiency, produces silicon wafers with good flatness, and is low in cost. However, it creates a damage layer several micrometers deep on the silicon wafer surface, leading to reduced wafer strength and increased susceptibility to fragmentation. Residual stress remains on the ground surface, causing wafer warping and complicating handling and subsequent processing. Subsequent processes are generally required to eliminate the damage layer and residual stress. Chemical mechanical polishing uses a combination of chemical and mechanical action to remove material, resulting in minimal damage to the silicon wafer surface. However, its disadvantages include low material removal rate and high operating pressure. Wet etching involves immersing a silicon wafer in an acidic chemical solution (HNO3/HF/HPO4) to remove the surface material through a chemical reaction. This process leaves the silicon wafer surface undamaged and free of lattice dislocations, significantly improving its strength and reducing warpage. However, it requires protection of the front side of the wafer, has weak correction capabilities for grinding marks, is unsuitable for processing bumped wafers, has a high etching rate (5-40 mm/min), uneven etching rate (5%-10% of the total etching amount), and causes environmental pollution. Atmospheric pressure plasma etching (ADP) is a newly developed dry etching technology that utilizes magnetic force control and operates under atmospheric pressure. In an argon atmosphere, the ADP system introduces CF4 gas into the plasma region, causing 100% decomposition. The CF4 reacts chemically with the material on the silicon wafer surface to generate SiF4. 4. Achieving material removal. During processing, the pressure generated by the Bernoulli effect suspends the silicon wafer above the plasma zone. Unlike wet etching, the front side of the wafer does not require tape protection, making it suitable for processing thinner wafers and wafers with protrusions. ADPE can remove the damaged layer on the back side of the silicon wafer caused by grinding, with a processing speed of 1-4 mm/min and a back-side removal depth of 50-100 mm. The surface smoothness after processing is better than that of wet etching. Dry polishing is a newly emerging technology for removing stress from silicon wafers. Its processing principle is similar to silicon wafer grinding, but the difference is that a polishing wheel made of fiber and metal oxides replaces the diamond wheel. Dry polishing can effectively remove residual stress caused by grinding on the back side of the silicon wafer, and it is low in cost, but the processing efficiency is low, with a processing speed of only 1 mm/min, and it is only suitable for removing shallow damaged layers. The back-side thinning process of silicon wafers. The original thickness of silicon wafers is generally 675-775mm, and the final thickness needs to be reduced to 100-200mm, sometimes even as low as 50mm. In the silicon wafer thinning process, it is generally not possible to grind the silicon wafer to a very thin size. This is because if the silicon wafer is directly ground to the thickness required for chip packaging, the breakage rate during transportation and subsequent processes will be very high due to the presence of a mechanical damage layer. Therefore, in practical applications, for a 200mm silicon wafer, if a 100mm thin wafer is required, most of the excess material is first removed by grinding, thinning the back side to about 180mm. Then, one or two of CMP, wet etching, ADPE, and dry polishing are used to eliminate the damage layer and residual stress caused by grinding, resulting in a damage-free wafer surface. Therefore, the back-side thinning of silicon wafers generally has four process schemes: back-side grinding + CMP, back-side grinding + wet chemical etching, back-side grinding + ADPE, and back-side grinding + dry polishing. 3 Three-wafer back-side grinding thinning technology 3.1 The principle of back-side grinding thinning of silicon wafers was already used in the 1970s for back-side thinning of silicon wafers with a diameter of less than 100mm by using the surface grinding on a rotary table method. As the diameter of silicon wafers increases, the requirements for back-side thinning of silicon wafers become higher and higher, and the rotary table grinding technology has certain limitations. In 1984, S. Matsui proposed the silicon wafer self-rotating grinding method and began to gradually replace the rotary table grinding method. The processing principle of silicon wafer self-rotating grinding method. A workpiece turntable slightly larger than the silicon wafer is used. The silicon wafer is clamped in the center of the workpiece turntable by a vacuum chuck. The inner and outer circumference centerlines of the working surface of the cup-shaped diamond grinding wheel are adjusted to the center position of the silicon wafer. The silicon wafer and the grinding wheel rotate around their respective axes to perform in-feed grinding. The grinding depth tw is related to the axial feed speed f of the grinding wheel and the silicon wafer rotation speed nw as follows: tw=f／nw (1) Advantages of silicon wafer self-rotating grinding method: (1) Ductile grinding can be achieved. When processing brittle materials, ductile grinding can be achieved when the grinding depth is less than a certain critical value. For self-rotating grinding, it can be seen from formula (1) that for a given axial feed speed, if the rotation speed of the worktable is high enough, an extremely small grinding depth can be achieved. (2) High-efficiency grinding can be achieved. It can be seen from formula (1) that by simultaneously increasing the silicon wafer rotation speed and the axial feed speed of the grinding wheel, a higher material removal rate can be achieved while maintaining the same grinding depth as ordinary grinding, which is suitable for large-mass grinding. (3) The contact length, contact area, and infeed angle between the grinding wheel and the silicon wafer remain unchanged, the grinding force is constant, the processing state is stable, and the phenomenon of convexity and edge collapse of the silicon wafer can be avoided. (4) The grinding machine only has feed motion along the grinding spindle direction, which is beneficial to improving the rigidity of the machine tool. (5) By adjusting the included angle between the grinding wheel axis and the workpiece axis, the non-parallelism between the grinding wheel axis and the worktable axis caused by the deformation of the machine tool can be compensated. (6) The grinding wheel speed is much higher than the silicon wafer speed, so the wear of the grinding wheel has little impact on the flatness of the silicon wafer. (7) Spin grinding processes one silicon wafer at a time, and the grinding feed is not limited by the unevenness of the machining allowance between silicon wafers. (8) Spin grinding equipment for silicon wafers has a compact structure, is easy to integrate into multiple stations, and can even be integrated with polishing equipment to achieve integrated grinding and polishing. Due to the above advantages, backgrinding of large-size silicon wafers with a diameter of 200mm or more now mostly adopts ultra-precision grinding technology based on the principle of spin grinding of silicon wafers. 3.2 The back-side grinding process of silicon wafers generally consists of two steps: rough grinding and fine grinding. In the rough grinding stage, diamond wheels with a grit size of 46#-500# are typically used, with an axial feed rate of 100-500 mm/min, resulting in a relatively large grinding depth, typically 0.5-1 mm. The purpose is to quickly remove most of the excess material on the back of the silicon wafer (approximately 90% of the machining allowance). In the fine grinding stage, the machining allowance is reduced to a few micrometers to tens of micrometers, using diamond wheels with a grit size of 2000#-4000#, with an axial feed rate of 0.5-10 mm/min. The main purpose is to eliminate the damaged layer formed during rough grinding, achieving the required thickness. In the fine grinding stage, the material is removed in a ductile-domain mode, significantly reducing surface damage to the silicon wafer. 3.3 Performance characteristics of back-side grinding of silicon wafers (1) Processing efficiency Grinding is the most efficient and lowest cost method for thinning the back side of silicon wafers. Grinding can quickly remove most of the processing allowance on the back side of the silicon wafer. For example, for a 300mm diameter silicon wafer with an original thickness of 775mm, the time required to reduce it to a thickness of 200mm is about 1 minute. (2) Processing accuracy Back-side grinding of silicon wafers can achieve extremely high thickness uniformity. For a 300mm silicon wafer, the thickness variation can even reach less than 0.5mm; the surface roughness Ra can reach several nanometers. (3) Surface and Subsurface Damage Grinding the back of a silicon wafer utilizes mechanical action to remove material, inevitably causing damage to the surface and subsurface of the wafer. Subsurface damage is one of the most important indicators of back-side thinning of silicon wafers. The surface damage after grinding consists of three layers: the top layer is an amorphous layer with microcracks, followed by a deeper lattice dislocation layer, then an elastic deformation layer, and finally the normal single-crystal silicon structure. The particle size of the abrasive wheel has the greatest impact on the degree of subsurface damage, while the equipment precision and grinding parameters also significantly affect subsurface damage. Generally, during rough grinding, the material is removed in a brittle fracture mode, leaving a damage layer with a depth of 20-30 mm and significant residual stress on the silicon wafer surface. In the fine grinding stage, the material is removed in a ductile mode, which eliminates the damage layer formed during rough grinding. The surface damage after fine grinding is significantly reduced, and its depth is generally less than 15 mm. In addition, due to the inconsistent edge height of the abrasive grains during grinding, grinding marks are also left on the silicon wafer surface. (mark). A large amount of data analysis shows that chips often break during bonding and testing. The reason for the breakage is often that the damage caused during the back thinning is not completely removed during subsequent etching or chemical mechanical polishing. (4) Warping deformation Grinding will generate residual stress on the silicon wafer surface, causing the silicon wafer to warp after back grinding, which often leads to silicon wafer breakage. Since the residual stress caused by rough grinding is large, the maximum warping usually occurs after rough grinding. Usually, wet etching, atmospheric pressure plasma etching, chemical mechanical polishing and other methods are needed to remove the damaged layer and residual stress in order to reduce silicon wafer warping. 3.4 Key technologies for back grinding of silicon wafers Since single crystal silicon is a typical hard and brittle material, in order to achieve high efficiency, ultra-precision and ultra-thin grinding of large-size silicon wafers, the following key technologies should be available: (1) High-precision, high-rigidity spindle system: Silicon wafer grinding machines should have extremely high static and dynamic rigidity and excellent thermal balance structure. Therefore, both the grinding wheel spindle and the workpiece rotary table spindle adopt high-precision, high-rigidity, and high-speed air bearing spindles with built-in servo motors. The radial runout of the grinding wheel spindle and the workpiece spindle is less than 0.02 mm. (2) High-precision micro-feed system: In order to achieve ductile grinding of silicon wafers, a small grinding depth is achieved by reducing the axial feed speed of the grinding wheel. This requires the feed motion of the grinding machine to have very small resolution and be precisely controlled. Currently, the minimum axial feed speed of the grinding wheel in advanced back-side grinding machines abroad can reach 1 mm/min. (3) The key technology for ultra-precision grinding of hard and brittle materials such as single-crystal silicon using ultra-hard abrasive wheels with fine grit is the performance of the grinding wheel. Cup-shaped diamond grinding wheels are used for back grinding of silicon wafers. The diameter is generally 350mm-200mm and the diamond grit is between 300# and 4000#. The grit of the grinding wheel is strictly controlled and the grinding wheel is made with a special binder, which has a long service life. (4) Precision positioning and clamping device for silicon wafers In order to safely and reliably transport and process thin silicon wafers, the front side of the silicon wafer is generally first bonded to a rigid support substrate with special double-sided tape, and then clamped on the workpiece turntable by a vacuum chuck. 4 New progress in silicon wafer back grinding technology Due to the changes in silicon wafer diameter and thickness and chip thickness, the main problems faced by silicon wafer back grinding technology are: (1) Improving the efficiency of silicon wafer thinning. The increase in the original silicon wafer thickness and the ultra-thinning of the chip increases the amount of material removed during back grinding of silicon wafers. As the main process for back grinding of silicon wafers, back grinding requires high processing efficiency. (2) Reduce surface and subsurface damage. Grinding-induced damage and residual stress greatly reduce the mechanical properties of silicon wafers and increase the risk of wafer breakage. To reduce damage and residual stress, finer-grained grinding wheels and smaller grinding amounts must be used. (3) Reduce or avoid silicon wafer warpage. Silicon wafers after back-side grinding will exhibit significant warpage deformation, and the thinner the wafer, the greater the warpage deformation. In subsequent processes such as wet etching and CMP to remove residual stress, the transport and handling of warped silicon wafers are very difficult, often leading to wafer breakage. Therefore, it is necessary to reduce grinding residual stress to reduce silicon wafer warpage. To solve the above problems, domestic and international research on back-side grinding technology for silicon wafers has been continuously carried out, and some new progress has been made, mainly in the following aspects: ◆a. Development of new types of ultra-precision grinding machines In recent years, the Tetraform grinding machine developed by Cranfield University in the UK possesses high static and dynamic rigidity and an excellent thermal balance structure, enabling high-speed, ultra-precision grinding under conditions of isolated environmental vibration and temperature. It achieves a surface roughness of Ra1-20nm when grinding single-crystal silicon, with a subsurface damage depth only 1-2% of that of conventional grinding, even less than the subsurface damage depth produced by polishing. The Super Silicon Research Institute and Disco Corporation in Japan have proposed a concept grinding machine with a "triangular prism-shaped pentahedral structure," which offers higher rigidity and better stability. Experimental results show that, under the same grinding depth conditions, its processing efficiency is four times that of ordinary silicon wafer grinding machines, resulting in better flatness and minimal surface damage on the ground silicon wafers. Hiroshi Eda and colleagues at Ibaraki University in Japan have developed an integrated grinding system based on the principle of self-rotating grinding. This system has two degrees of freedom (axial feed of the grinding wheel spindle and radial feed of the workpiece spindle). Grinding is achieved using an air-hydrostatic guideway and an air spindle support. The radial runout of both the grinding wheel spindle and the workpiece spindle is less than 0.02 mm. The ultra-precision positioning and feed mechanisms can achieve a feed rate of 0.5 mm/min. A super-magnetostrictive micro-drive device adjusts the angle between the grinding wheel axis and the workpiece axis to control the surface accuracy of the silicon wafer. This system can complete ductile grinding and polishing-like grinding of silicon wafers in a single operation. For silicon wafers with a diameter of 300 mm, it achieves a surface roughness Ra < 1 nm, TTV < 0.2 mm, and reduces the surface damage layer to 120 μm. Energy consumption is reduced by 70% compared to traditional processes. ◆b. Research on ultrafine-grained diamond grinding wheels and their application technologies H. Ohmori et al. in Japan applied online electrolytic dressing (ELID) technology to the self-rotating grinding process of silicon wafers, using cast iron fiber-bonded micronized diamond grinding wheels with a grit size of #10,000-#3,000,000, and still achieved stable grinding. Grinding silicon wafers with a #3,000,000 wheel (average grit size 8nm) yielded a surface with RMS ≤ 0.47nm, very close to the surface obtained by chemical mechanical polishing. ◆c. Using a dicing-before-thinning process The warping deformation of the silicon wafer after back-side grinding can cause difficulties in subsequent wafer transport and clamping positioning, and is prone to breakage during dicing. Disco developed DBG (Dicing Before Thinning) technology. DBG (Deep Dicing) technology involves cutting a slit to a certain depth on the front side of the silicon wafer before back-side grinding. This process avoids wafer warping and reduces the risk of breakage during the transport of large, ultra-thin silicon wafers. Using DBG technology, a 300mm silicon wafer can be thinned to 50µm. Recently, the concept of DbyT (Dicing-by Thinning) has emerged. Similar to DBG, it involves cutting a slit mechanically or chemically before thinning. The difference is that after thinning to a certain thickness using grinding, ADP (Advanced Dicing Processing) abrasion technology is used to remove the remaining machining allowance, achieving automatic separation of the bare die. ◆d. Achieving Back-Side Thinning Process Integration To reduce the number of times silicon wafers are handled and clamped, thereby improving processing efficiency and reducing breakage, advanced silicon wafer back-side grinding machines employ a multi-spindle indexing table structure. Rough and fine grinding can be achieved by clamping the silicon wafer once on the same machine. Ultra-precision feed and positioning mechanisms control minute grinding depths. An automatic spindle angle adjustment device ensures wafer flatness. An online thickness measurement device effectively controls wafer thickness. Furthermore, dry-in/dry-out cleaning and drying systems, as well as robotic arms for automatic wafer loading and unloading, are included. In recent years, some Japanese companies have also developed grinding and polishing machines that integrate silicon wafer back-side grinding with CMP or dry polishing. Tokyo Seimitsu's PG300/PG200 series grinding machines achieve rough grinding, fine grinding, and polishing of silicon wafers with only one clamping on the same machine, achieving rapid thinning and removal of damaged layers and residual stress.