WCMP is the most important layer in electron beam inspection applications. Its main functions include enabling engineers to identify device leakage and poor contact issues. EBI (Electron Beam Inspection) can help improve yield, reduce the development cycle of semiconductor IC technology, and shorten the time required to increase yield.
The figure below illustrates the Metal-1 Single-Damascene (MSD) copper interconnect technology. Silicon carbon nitride (SiCN) is a dense material that can be used to replace silicon nitride as a barrier layer to prevent copper diffusion, and it can also be used as an etch stop layer (ESL) in copper interconnect processes. Compared to silicon nitride (k=7~8), SiCN has a lower dielectric constant (k=4~5), therefore, using SiCN can reduce the overall dielectric constant of the ILD layer. The most commonly used low-k dielectric material is PECVD SiCOH, which is widely used in interconnect processes. The barrier layer and copper seed layer are deposited using PVDI, and plasma ionization of metals is typically used to improve the coverage of the bottom layer. Because the mechanical strength of low-k dielectrics is lower than that of silicate glass, the downward grinding force of copper CMP with low-k dielectrics is lower than that using USG or FSG materials. After Metal-1 CMP, electrical characteristics are first measured in the test structure. Tiny probes contact the probe contact area of the test structure, and the electrical performance of the device is tested using voltage or current . To avoid copper oxidation and reduced yield, there is a time limit between copper CMP and capping deposition. Therefore, defect detection using optical inspection and electron beam inspection systems is usually performed after capping deposition.
Dual damascene processes are commonly used for copper metallization and require two dielectric etching processes. There are at least three different methods to form the vias required for dual damascene copper metallization. One method is to etch the trench first, then the via (see figure below). Another method is to embed a hard mask, first etching the via and stopping at the etch stop layer, then using a trench mask to simultaneously form the via and trench (see figure below). The figure below illustrates the trench-first method. Both via-first and trench-first processes are used in copper metallization processes in IC manufacturing.
In low-k dielectric etching processes, the etching stop layer defines the depth of vias and trenches by the optical signals emitted from etching byproducts in the plasma. PE- TE OSUSG and SiCN can be etched using F/O. For buried hard mask dual damascene etching (see figure below), high selectivity of the low-k dielectric for SiCN is required.
Tantalum (Ta), tantalum nitride (TaN), and combinations thereof can be used as copper barrier layers to prevent copper from diffusing through the dielectric layer into the silicon substrate, which can damage transistors . Chemical electroplating (ECP) with a copper seed layer fills narrow trenches and vias with large amounts of copper. It is crucial that a large amount of copper is electroplated immediately after the copper seed layer deposition because copper can rapidly self-anneal even at room temperature. Annealed copper seed layers have larger grain sizes and rougher surfaces, leading to voids in the trenches and vias during ECP and reducing yield.
After copper plating, the wafer is annealed in a furnace at approximately 250 degrees Celsius to increase grain size and reduce resistivity . Once Cu and Ta are removed from the wafer surface via CMP (Chemical Metal Processing), only metal remains in the trenches and vias to form interconnects. The endpoint of the metal CMP process is typically determined by the reflectivity of the wafer surface, as most metals have very high reflectivity. Once the metal is polished to the dielectric surface, the reflectivity decreases significantly, indicating that the etching has reached its endpoint.
