Abstract: A DC servo motor controller is designed in an FPGA using the VHDL hardware description language. It contains four PWM controllers, each assigned an ID. When the address line `Addrcss` selects an ID, it indicates operation on the PWM controller. The address line signals are latched using the ALE and WR signals. The motor encoder capture unit obtains the motor encoder signal and sends it to the MPU for reading via the bus controller. This determines the motor speed. Keywords: FPGA; Hardware description language; DC servo motor controller Introduction DC servo motor processors, such as microcontrollers and DSPs, have the ability to generate PWM signals and capture motor encoder signals, but the number of PWM signal channels and encoder capture channels for ICs is limited. This makes it difficult to meet the requirements for servo control of multiple DC motors. Therefore, an FPGA-based DC servo motor controller is designed. 1. Controller Composition A four-channel PWM generator and encoder pulse capture unit are designed inside the Cyclone EP2C5T FPGA. The number of PWM signal channels and encoder pulse capture units can be adjusted as needed using the VHDL hardware description language. See Figure 1. The system includes a bus and four PWM controllers, four pulse capture units, and frequency dividers 1 and 2. The bus controller uses WR, RD, and ALE signals to latch the FPGA's internal address and control the 8-bit OUTPUT and INPUT buses. An external 20 MHz active crystal oscillator is connected to the FPGA. The clock signal is divided by frequency divider 1 to obtain a 20 kHz square wave signal with a 50% duty cycle. The four PWM controllers use this signal as a reference to generate four PWM signals with a frequency of 20 kHz and adjustable duty cycles. These four PWM signals can be independently controlled using four address lines. The four pulse capture units capture the motor encoder pulse signals. The captured pulse values ​​are read out to the 8-bit I/O port via the bus controller. Frequency divider 2 divides the 20 kHz square wave signal by 20000 to obtain a 1 Hz square wave signal with a 50% duty cycle, directly driving an LED to indicate the system status. The internal logic of the EP2C5 FPGA is implemented using VHDL hardware description language in the Qoartus11 6.0 environment. 2. VHDL Design of Servo Motor Controller 2.1 Bus Controller Design Writing to the servo motor controller involves PWM adjustment values, while reading from the motor encoder involves motor encoder values. Therefore, a bus controller needs to be designed to complete the above process. The FPGA-based DC servo motor controller provides a bus interface for external processors (such as microcontrollers). Similar to the multiplexing of address and data lines in an 8051 MCU, a bus controller was designed. The control bus includes WR, RD, and ALE; the data/address bus is an 8-bit I/O. The bus controller logic circuit is shown in Figure 2, implemented using two 74244 chips. The WR and RD signals cause the input/output bus to alternately enter a high-impedance state, realizing the writing or reading of servo motor controller data. 2.2 PWM Controller Design The VHDL hardware description language for the PWM controller is as follows: Since there are 4 PWM controllers in the design, each controller is assigned an ID. In the above program, setAddress is the ID of the PWM controller. When the address line Address is selected with this ID, it indicates that the PWM controller is being operated on. The address line signals are latched using the ALE and WR signals. The count is incremented by 1 each time the clk signal rises. The duty cycle of the PWM signal is adjusted by comparing the values ​​of count and databus. PWM controllers can be added as needed, provided FPGA resources allow. 2.3 Motor Encoder Capture Unit Design: After obtaining the motor encoder disk signal, the motor encoder capture unit sends it to the MPU for reading via the bus controller to determine the motor's rotation speed. The VHDL hardware description language program source code is as follows: Multiple encoders are defined using setAddressL and setAddressH to define the address of each encoder. When the address is the same as setAddressL and setAddressH, the encoder capture unit is selected. Simultaneously, RD and ALE control are used to transmit the captured data to the bus. 2.4 Frequency Divider 1 Design: The FPGA EP2C5T global clock signal is connected to an external 20MHz active oscillator. To obtain a 20kHz PWM signal, a frequency divider was designed in the EP2C5T using VHDL. The VHDL program is as follows: The principle of frequency divider 2 is the same as that of frequency divider 1. The 20kHz square wave signal is divided by 20000 to obtain a 1Hz square wave signal. 3. Conclusion A DC servo motor controller designed in an FPGA using the VHDL hardware description language can meet the servo control requirements of multiple DC motors. This controller can operate stably and reliably in a 4-channel DC servo motor control system.