Abstract: This paper explains the reasons for using EP9312 to construct an embedded system for banking and taxation, and compares EP9312 with other embedded processors. Based on the characteristics of EP9312 and system requirements, an embedded system hardware design scheme based on EP9312 is proposed. The technical specifications of the system and its components such as Super I/O, PHY, interface level converter, Flash, SDRAM, and Boot-loader are introduced. The system is mainly used in high-end printers, computer terminals and high-end cash registers. Keywords: banking and taxation; EP9312; hardware design; embedded system 1 Concept and characteristics of embedded systems Embedded systems combine the system circuit of a microprocessor or microcontroller with its dedicated software to achieve the highest system operating efficiency. An embedded system is defined as a small computer system (compared to a PC). Due to its small size, its hardware and software structure and application scope are quite different from those of a PC. Its characteristics can be summarized as follows: (1) It usually performs specific functions; (2) It is based on a microcomputer and peripherals; (3) It has strict timing and stability requirements; (4) It operates in a fully automatic cycle. Embedded systems are purposeful or targeted, and their development revolves around the product and its specific functions. They must be "tailor-made" in both hardware and software to maximize efficiency. The embedded system designed in this paper is mainly used for financial and tax products. 2 Overall Design 2.1 CPU Selection This paper uses the Cirrus Logic EP9312 embedded processor. The EP9312 is an ARM9 series processor, which is the best hard macrocell in terms of high performance and low power consumption. It has a five-stage pipeline and provides a Harvard architecture of 1.1 MI/s/MHz. Its predecessor, the ARM7 series processor, features embedded ICE-RT logic, very low power consumption, and provides a three-stage pipeline and von Neumann architecture of 0.9 MI/s/MHz. Because this system is mainly used to develop advanced computer terminals, set-top boxes, high-end printers, etc., a fast computing speed is required. The ARM7 is mainly used for price- and power-sensitive consumer products, and its computing speed is relatively slow. Therefore, this design system chooses the ARM9 series. The ARM9 series CPUs also include the EP9307 and EP9315. The EP9307 has a basically the same functional structure as the EP9312, lacking only one IDE interface but adding graphics acceleration functionality. Since financial and tax products often require a large number of GPIOs, and the EP9312 can be easily designed with more GPIOs compared to the EP9307. The EP9315 adds a PCMCIA interface and graphics acceleration functionality to the features of the EP9312, but these are not essential features for financial and tax products. After comprehensive consideration, this system selected the EP9312. 2.2 Technical Specifications Based on system research and product cost considerations, the technical specifications of the embedded system are as follows: ● Cirrus Logic EP9312 as the main processor; ● 32MB NOR Flash; ● 64MB SDRAM; ● Display format: Western characters: 24x12 dot matrix, Chinese characters: 24x24 dot matrix, 26 rows, 80 columns. Alternatively, in Western languages: 16x8 dot matrix; in Chinese: 16x16 dot matrix, 26 rows, 80 columns; ● Multiple TFT display modes including 800x600x16bpp and 1024x768x16bpp, supporting single or dual scanning; ● One parallel port; ● Five serial ports; ● Two PS/2 ports; ● One 1/10/100 Mb/s Ethernet interface. Supports TCP/IP protocol; ● One USB Host and one USB Slave interface. 2.3 System Composition The EP9312 has integrated many functions required for embedded systems. To meet the requirements of financial and tax products, the following hardware has been added: SuperI/O devices (including two UARTs, one parallel port, and two PS/2 interface controllers), network PHY interface devices, interface level converters, Flash, SDRAM, etc. The PCB board uses a 4-layer design, with the signal layer on the surface. The power and ground layers are deeply embedded in the inner layers of the motherboard, making it less susceptible to power supply noise interference, especially in high-frequency circuits, thus providing good anti-interference capabilities. The basic structure of the system is shown in Figure 1. 3. Module Function Description 3.1 CPU The EP9312's core is an ARM920T with a clock speed of 200MHz and a 100MHz internal bus. It has 16KB of instruction cache and 16KB of data cache, and integrates many functional modules, including: an LCD controller, three USB Host controllers, three serial port controllers, an Ethernet MAC, EIDE, and an AC'97 interface. The EP9312 includes an MMU, supports the TCP/IP protocol, and provides a quick way to develop various character and graphic functions. This design fully utilizes these integrated functions, reducing the number of external components. 3.2 RESET Module The system's RESET module provides the system with start and reset signals, marking the beginning of system operation. This system uses a MAX708CSA as the reset device, designed as a user-controlled restart button. A RESET signal is sent to the CPU's RSTON pin, the Flash module, the JATG module, etc. Another MAX708CSA is used as the power-on button. A POR signal is sent to the CPU's PRSTn pin, as shown in Figure 2. 3.3 System Clock Module The system clock module generates 20 independent clock frequencies to meet the requirements of different independent logic sections of the EP9312. All these clock frequencies originate from an external low-frequency crystal oscillator. This allows the processor speed, bus speed, and video speed to be different and independent of each other. The EP9312 provides two interfaces to connect to an external crystal oscillator with frequencies of 32 kHz (real-time clock) and 14.7456 MHz. To obtain a sufficiently high clock frequency, the EP9312 also provides two PLLs to boost the 32 kHz and 14.7456 MHz frequencies to a sufficiently high level (14.7456 MHz, with a maximum frequency of 400 MHz). 3.4 Debug Port (JATG) Module The EP9312 provides a JTAG debug interface with 6 test scan chains. This interface implements debugging functions through 5 external control signals: TDO—Test Data Output; TDI—Test Data Input; TMS—Test Mode Selection; TCK—Test Clock; nTRST—Test Reset. Since the EP9312 integrates these JTAG signals, these signal lines can be brought out to extend the JTAG port on the board, enabling communication with a JTAG debugger. 3.5 Memory The EP9312 contains an SDRAM controller, providing a high-speed storage interface for various storage devices, including SDRAM, Synchronous Flash, and Synchronous ROM. The CPU already has an SDRAM controller, so the system does not require an external SDRAM controller; simply using a suitable SDRAM memory and connecting it to the EP9312's dedicated SDRAM signal lines is sufficient. This system uses two IS4216400B 16-bit data bus SDRAM devices to form a 32-bit data bus 16 MB storage system. If needed in the future, the system can be easily expanded to 32 MB SDRAM simply by replacing the 8 MB device with a 16 MB device. The Flash device used in this system is the Intel TE28F320J3D-75. This device uses a 56-pin TSOP package, and the 32 MB storage space consists of 32 128KB erase blocks. This Flash uses 25 address lines and 16 data lines, and can be accessed in 8-bit or 16-bit mode via the BYTE signal. This system uses 16-bit access, so this signal line is connected high, and the AO address line is grounded. OE/WE are read/write signals, directly controlled by the read/write control lines of the EP9312. In the system, the Flash chip select signals CE2 and CEL are grounded, and CEO is controlled by the two chip select signals CSO and CS6 of the EP9312 via jumpers, as shown in Figure 3. The Flash in this system needs to be designed to support 2 MB, 4 MB, and 8 MB circuits; only different capacity devices need to be soldered. This approach caters to the needs of different users. For example, users with CF cards only require 2 MB of Flash memory. In this case, careful selection of the Flash and SDRAM models is necessary, along with corresponding design of the address and data buses. 3.6 PS/2, serial, and parallel ports are expanded via Super-I/O, as shown in Figure 1. The Super-I/O selected is the Winbond W83977ATF. This device provides two serial ports, one parallel port, a PS/2 keyboard/mouse interface, and 23 GPIOs. The WAITn delay signal of the EP9312 is used to match the speed of the ISA bus and the memory bus. Together with the three serial port controllers provided by the CPU, the system has a total of five serial ports. 3.7 Network: The EP9312 contains an internal Ethernet MAC, requiring only one PHY and implemented through the VT6103L. 3.8 Display Circuit: The display circuit design depends on the different display screens. This system is designed to support five screen types: TFT, CSTN, DSTN, LVDS, and VGA. The EP9312 outputs digital signals, including 18-bit data, vertical frequency, horizontal frequency, clock, and brightness control signals. For TFT and CSTN screens, they can be directly connected to the EP9312's built-in interface. However, it's important to note that when initializing the color lookup table for CSTN, the R and B color codes must be swapped. A level converter is required when connecting to a TFT screen. For DSTN, this system uses a Sharp LM121VB1T02 screen, a monochrome screen with 4 pixels per clock cycle, one pixel per signal. After consulting the EP9312's output pixel conversion table, it was found that the dual-scan 4-pixel-per-clock-cycle mode is not suitable for this screen. Therefore, this system uses a dual-scan 8-pixel-per-clock-cycle mode and selects suitable signals to drive the screen, requiring a level converter. Currently, TFT interface screens are not mainstream; LVDS interface screens are more widely used. For the LVDS interface design, this system uses a DS90C383MTD converter. For a color CRT, three D/A converters and level converters are required; for a monochrome CRT, only one D/A converter and level converter are needed. Connecting to a VGA screen requires a dedicated device, such as the ADV7123. The display circuit block diagram is shown in Figure 4. 3.9 Power Supply The EP9312 requires four different power supplies: RVDD (3.3 V), CVDD (1.8 V), VDD_PLL (1.8 V), and VDD_ADC (3.3 V). In addition to the 3.3 V power supplies, other components on the board also have 5 V power supplies. The total system input voltage is 12 V, which is transformed to 5 V by a transformer, then converted to 3.3 V by an LT176ET-3.3 converter, and finally converted to 1.8 V, the EP9312 core voltage, by an LT176ET-1.8 converter. 3.10 GPIO Allocation The EP9312 has 16 enhanced general-purpose I/O pins with interrupt capabilities. Since embedded systems in the financial and tax sectors typically do not require an IDE interface, the IDE interface I/O is designed as GPIO. Together with other design elements, this adds a total of 49 optional general-purpose I/O pins. 3.11 Bootloader The bootloader is the first piece of software code to run when the system powers on. The entire system's loading and startup tasks are entirely handled by the bootloader. Simply put, the bootloader is a small program that runs before the operating system kernel or user application. Through this small program, hardware devices are initialized, and a memory space mapping is established, thus bringing the system's hardware and software environment to a suitable state to prepare the correct environment for the final call to the operating system kernel or user application. The EP9312 provides 20 bootloader modes, selected via jumper combinations of EECLK, EEDAT, LBOOTI, LBOOTO, ASDO, and CSn [7:6]. During debugging and production, this system uses a 16-bit serial boot method. The corresponding EECLK, EEDAT, LBOOTI, LBOOTO, ASDO, CSn[7:6] selection methods are: l, 1, 0, X, 0, 1. At this time, the CPU starts through the 4 KB program already embedded on the chip, initializes the CPU and serial port, and downloads the user program to the Flash through the serial port. When the system is working normally, it starts directly through the Flash. The program code is read directly from the Flash and run. This design uses the former to write the operating system and application into the Flash, and uses the latter to enable the normal operation of the embedded system. 4 Conclusion This paper introduces a hardware design scheme for a bank tax embedded system based on EP9312. After testing, all parts of the system can work normally and realize the predetermined functions. Compared with the previous embedded system platform, this system has high integration, small motherboard area, many peripheral interfaces, low cost, and fast running speed. It is a product with high cost performance and can provide a good platform for the development of embedded products. It is mainly aimed at embedded products such as computer terminals, passbook printers, registration machines, and POS machines.