Modern computing servers don't consist of stacked chips; instead, they have computing cards inserted side-by-side into slots. Most current computing servers hold 8 or 16 computing cards per unit.
The core of a computing card is, of course, the computing chip, which is paired with large-capacity, high-bandwidth memory, cache, and a CPU for scheduling. To facilitate data transmission, a high-speed channel is used, which is the role of PCIe (High-Speed Serial Computer Expansion Bus standard) in the system: to provide a bus channel.
Image: Schematic diagram of computing power card
PCIe is widely used in data processing. For example, the CPU controls and schedules the chipset to work using the PCIe bus. The interconnection between computing cards may also use the SerDes bus. The calculated data is stored in the SSD hard drive using the PCIe bus. The CPU and Switch chip inside the switch in the computing center use the PCIe bus.
Figure: Application of PCIe bus in AI heterogeneous computing systems
Therefore, PCIe is essentially a universal bus standard that connects the heterogeneous computing systems behind AI. By adopting the PCIe interface, developers don't need to worry about the interconnection between different components of an AI system, such as computing chips, accelerator chips, memory chips, storage chips, gateway chips, and switches.
PCIe empowers the rapid development of current artificial intelligence systems in several ways, including the following characteristics:
1. High-efficiency transmission
2. High scalability
3. Real-time processing capability
4. Continuously optimized low-power performance
Since PCIe connects to the core chips in the system and is responsible for data transmission, its performance and reliability are crucial. In actual testing, the first step is to test the peak upload and download speeds of the PCIe interface, as well as the stable transmission speed, which is key to ensuring efficient computing. Next, the electrical characteristics of the PCIe interface are tested, including transmission power consumption and the specific performance of low-power functions such as high-speed logic wake-up, as shown in the following figure:
Image: Keysight Technologies PCIe Test Topology Diagram
In addition, PCIe interface stability also requires testing hot-swapping capabilities, isolation, and EMC performance. Of course, some manufacturers are no longer satisfied with PCIe's transmission speeds and have developed their own connectivity standards. For example, Intel offers Xe Link for interconnecting computing cards, a new protocol based on PCIe 5.0 extensions; NVIDIA has developed NVLink as an alternative to PCIe, offering bandwidth and energy efficiency several times that of PCIe 5.0. These self-developed solutions present greater testing challenges. For Keysight Technologies, regardless of whether the PCIe protocol or a self-developed high-speed interconnect protocol is used, our solutions can meet the relevant testing requirements, as shown in the following diagram:
Image: Keysight Technologies PCIe 6.0 end-to-end testing solution
