Abstract: This paper presents an Ethernet switch based on the AT89818 switching chip. The AT89818 is used as the core switching chip, and the AT89C52 is used as the system configuration and control chip. A three-wire EEPROM stores the system configuration data. The PHY uses two 8-port 10M/100M Fast Ethernet physical layer transceivers M88E3080, providing 16 multi-port 10M/100Mbps RJ-45 Ethernet ports. Keywords: AT89818, AT89C52, Ethernet port switch Introduction In recent years, network technology has developed rapidly, and Ethernet dominates the market. This design uses Atan's AT89818 switching chip as the core chip and the AT89C52 as the system configuration and control chip. The switch provides excellent flexibility and ease of handling for Fast Ethernet upgrades, offering 16 multi-port 10M/100Mbps RJ-45 Ethernet ports. The switch automatically detects the speed of connected devices, allowing 10Mbps and 100Mbps devices to be used on the same switch without replacing existing network infrastructure. 1. System Functions The system conforms to the IEEE 802.3-802.3u standard, with 16 ports for 10/100Mbps multiplexing (using shielded RJ-45 connectors). The system has an address table capable of storing up to 8K MAC address entries and features store-and-forward switching, enabling it to automatically learn and store addresses from the MAC address table. It has a shared-memory dynamic O/I buffer, ensuring fast and error-free packet storage and forwarding. It adopts a plug-and-play configuration and automatic learning method, supports half-duplex and full-duplex modes, and has an MDI port for cascading. Key technical specifications include a maximum forwarding rate of 14,880pps/10BASE-T and 148,800pps/100BASE-TX. Maximum filtering rate: 14,880pps/10BASE-T; 148,800pps/100BASE-TX. 2. System Composition This switch system uses the AT89818 as the core switching chip; the MCU uses the AT89C52 for control and system settings, and is already connected to the computer; the EEPROM uses the AT93C46 to store the initialization data required when the switch starts up; the SRAM uses a 64K×64-bit W25P243A; PHY0 and PHY1 use 8-port DSP 10/100 PHYs; JACK0 and JACK1 are RJ-45 connectors. The system structure is shown in Figure 1. 2.1 AT89818 The AT89818 is the center of the entire hardware system and the core switching chip. The AT89818 can have up to 18 10M/100Mbps multiplexed interfaces, one or more of which can be bundled. The chip has an address table with 8192 MAC address entries, and VLANs can also be configured via EEPROM. Features include: ◇ Support for store-and-forward; ◇ 1522B buffer per VLAN packet; ◇ Support for aging-in and 802.3x flow control; ◇ Seamless connection to 64K×64-bit or 128K×64-bit SRAM; ◇ Broadcast storm control; ◇ Two MAC address-based bundling groups, each with 2-6 ports; ◇ Support for port-based VLANs configured via EEPROM; ◇ Port speed, half-duplex or full-duplex mode, bundling mode, VLAN settings, etc., can be configured via EEPROM. 2.2 MCU (AT89C52) The AT89C52 is used for system setup and control. The MCU can communicate with the computer via serial port, and control and manage the switch through the computer; at the same time, it and AT89818 alternately obtain control of the EEPROM. When the switching chip hands over control of the EEPROM to the MCU, the MCU reads and writes to modify the EEPROM. After the modification is completed, the MCU can hand over control to the switching chip, and the switching chip will read the configuration data from the EEPROM again. 2.3 Other devices (1) EEPROM The three-wire CMOS device AT93C46 is used. The data format of the EEPROM can be selected as 64 ×16 or 128 ×8 by setting the ORG pin high or low. It is connected to the MCU through CS, SK, DI, DO, and the MCU can read and write the data stored in the EEPROM. (2) PHY The M88E3080 is used. It is an 8-port 10M/100Mbps Fast Ethernet physical layer transceiver with higher signal-to-noise ratio and lower power consumption. It is a product of Marvell Semiconductor Inc. (3) SRAM The W25P243A is used. It is a 64K×64 piplined CMOS high-speed static RAM, a product of Winbond Electronics. 3. Design of Key System Circuits 3.1 System Clock Design Since the clocks of both PHY chips are 50MHz, while the clocks of the SRAM and AT89818 are 75MHz, this is already considered a high-speed digital circuit design. Therefore, signal integrity must be considered during the design. As shown in Figure 2, the clock drive capability can be increased by using a 74LVT244 buffer, generating two in-phase, minimally delayed, and consistent clock outputs to the two PHYs, ensuring signal integrity. Additionally, in the PCB design, high-speed signal traces should be kept as short as possible to ensure the integrity of the system signal design. 3.2 System Design for Control Between MCU, EEPROM, and AT89818 The connection between the MCU and AT93C46 is shown in Figure 3. The MCU can read and write to the AT93C46 via EDO, EDI, ESK, and ECS; simultaneously, EDO, EDI, ESK, and ECS are also connected to the DO, DI, SK, and CS of the AT89818, respectively. The AT89818 and MCU exchange control of the EEPROM via E2TR. When E2TR is low, the AT89818 reads configuration data from the EEPROM via DO, DI, SD, and CS; when E2TR is high, these four signal lines of the AT89818 are in a high-impedance state, and control of the EEPROM is handed over to the MCU, which can then modify the data in the EEPROM. E2TR must remain low for 30ms after a system restart. 3.3 Connection of AT89818 with PHY and SRAM The connection between the AT89818, M88E3080, and SRAM is shown in Figure 4. MDC is the 1MHz clock output from the switching chip, used to drive the PHY chip. To increase drive capability, a buffer can be considered first. MDIO manages the DATA lines used by the PHY chip for the switching chip. 4. Application Prospects This switch is a high-performance, low-power network device with Fast Ethernet switching capabilities. In recent years, network development has been rapid, and many communities are considering fiber-to-the-home (FTTH) during construction. This device, with its economic, practical, and efficient advantages, can fully meet the needs of a wide range of users. References 1 ATAN. ​​AT89818 18 Port 10/100 Base Ethernet Switch controller. 2000 2 Atmel Corporation. MOS 8-bit Microcomputer with 8K Bytes Flash AT89C52 Datasheet. 1999 3 Atmel Corporation. AT93C46/56/57/66 Datasheet 4 Marvell Semiconductor Inc. 8-Port DSP Fast Ethernet PHY