I. Introduction
Electric drive inverters are recognized as the core components of hybrid vehicles and electric vehicles. From the initial tens of kilowatts to the current hundreds of kilowatts, their requirements for rated power are getting higher and higher. Medium and high power inverters require the nominal current of the power module to be as high as hundreds to thousands of amperes. Such high current can only be achieved by connecting multiple bare dies in parallel, sometimes multiple sub-modules (integrating multiple bare dies on the same package substrate), or even multiple power modules[1].
In this context, weight, size and cost are the main factors that constrain the design of power modules. The three-phase half-bridge inverter solution that was initially designed using IGBTs has become very popular. Currently, the design of inverters using silicon carbide power modules with higher performance is a new trend. Power module design is usually a trade-off between thermal performance and electrical performance. A well-designed power module can distribute current evenly between the upper and lower bridge arm switches and between the dies inside the switches, provided that their static parameters are not too different. In addition, a good circuit layout means that thermal stress can be evenly distributed only if the mutual heating effect between dies is reasonable[1].
This paper introduces the development steps and process of a continuous operation temperature measurement system for an electric drive inverter module, and analyzes the thermal imbalance phenomenon between parallel silicon carbide dies that affects the service life of the power module. Parasitic elements and static parameters (e.g., on-state resistance and threshold voltage) caused by circuit layout are the main factors causing thermal imbalance of parallel devices. Paper [2] discusses in detail the asymmetry of circuit layout, which affects the gate-to-source loop, causes series inductance, and leads to drive loop mismatch, thus seriously affecting the dynamic performance of parallel devices.
Paper [3] describes how to analyze the thermal imbalance problem of the power module under steady state using infrared thermal imager images. Although the on-state resistance distribution range is an important static parameter, the relationship between resistance and temperature will compensate for the distribution range of the on-state resistance. In fact, the chip temperature rise will alleviate the thermal imbalance caused by the natural distribution range of drain-source on-state resistance.
This paper will focus on another key parameter: threshold voltage (Vth), which has a great impact on the switching performance and thus affects the energy loss of the power switch. The difference in threshold voltage Vth between two parallel chips will lead to energy consumption imbalance, which will ultimately affect the performance of the entire power module. Paper [4] describes in detail the impact of Vth on the switching energy consumption and proves that when Vth increases by 500mV, the power dissipation in the on state may increase by as much as 40%.
Based on this argument, we believe it is necessary to establish a temperature measurement system capable of directly measuring switching temperatures under normal operating conditions to evaluate and characterize the heat dissipation performance of different dies within a power module. This requires not only minimizing the range of process parameters, including the threshold voltage Vth, on the production line, but also taking further improvement actions at the module assembly level based on the minute differences between the two closest chips within the module. We used this concept to assemble two different power modules: the first module, called GAP1, has a maximum internal die threshold voltage Vth range of 250mV (around an average of +/- 125mV), and the second module, called GAP2, has a maximum Vth range of 500mV (around an average of +/- 250mV). Testing was conducted using two different switching frequencies: the typical operating frequencies of the electric drive inverter, 8kHz and 12kHz. It is well known that the increase in power dissipation is proportional to the switching frequency.
A. Experimental setup
Our primary goal was to design and develop a temperature measurement system that would allow us to measure the temperature of power chips in environments more closely resembling the actual applications of electric drive inverters. Therefore, we had to begin with suitable mechanical components, as well as hydraulic, electrical, and electronic components, ensuring all components were aligned with this objective. The following diagram shows the block diagram of the final, implemented temperature testing system.
The hydraulic component of the temperature measurement system consists of a chiller, inlet valve, and outlet valve. Coolant circulates within the hydraulic pipes to dissipate heat from the device under test. The inlet valve temperature and flow rate, as well as the dimensions of the water jacket (tank), are crucial parameters determining the inverter's size, as they directly affect the packaged RTH thermal resistivity. The coolant is a 50%-50% mixture of ethylene glycol and water, a common coolant preparation method in inverter cooler circuits. To measure the coolant flow rate, a flow meter is connected before the device under test; in our experiment, the coolant flow rate was set to 3.7 liters per minute. A thermometer is used to detect when the coolant temperature at the power module's inlet valve reaches a reference temperature of 65°C. An aluminum heat sink dissipates heat from the power module, and the power module's gate signal is provided by a dedicated gate driver board. Figure 2 shows the temperature measurement experimental setup.
Below is the equipment list.
Table 1: Test Equipment
B. Design of the temperature measuring device and gate driver board
We performed thermal analysis on a silicon carbide three-phase power module operating at a continuous high frequency. Specifically, by disconnecting the middle bridge arm of the power module and connecting the AC terminals of bridge arm U and bridge arm W to a 1.2mH inductive load, a full-bridge topology was obtained (Figure 3).
How to implement the drive module through a multi-layer structure is a key factor to consider when developing a temperature measurement system. The first stage (power supply) utilizes a DC-DC boost converter to provide +18V and 5V voltages, which are required for switching operation. The second stage (main board) contains drivers and on/off resistors to drive the charge injection gate-source capacitors to prevent the device from reaching its breakdown voltage during switching. The following is a 3D model of these boards.
The final stage is the control module implemented by the Nucleo STM32 microcontroller board. This module uses a unipolar PWM control method, driving the switches on both diagonals with the same signal. A complementary signal and the required dead time are used to drive the power switch on the second diagonal. The duty cycle of the PWM signal is set according to the load conditions and actual operating conditions to obtain a sinusoidal current waveform with the peak current meeting the design requirements. Figure 4 shows the relevant waveforms of the PWM complementary signal and the load current (460 A Imax).
The gate driver board is mounted on top of the power module, as shown in the figure above. The two boards are pyramid-shaped and complementary in structure, connected together by pin headers to minimize trace distance, parasitic elements on the driver board, and signal propagation delay.
The image below shows the testing tools used, as well as the DC bus and microcontroller board. Because high-frequency current flows through the bus, special attention should be paid to the correct bus dimensions during the design phase. There are two openings on the board for direct observation of the chip under test and for measuring the junction temperature (TJ) using an infrared thermal imager.
The characteristics of the SiC power module under temperature measurement are as follows: typical on-state resistance RdsON = 1.9mΩ (per switch) at 25℃, nominal current Iphase = 340A, and breakdown voltage Vb = 1200V. Figure 7 shows one arm of the full-bridge converter: each switch consists of eight parallel-connected bare chips. In the figure below, we can see the internal circuit layout of the device under temperature measurement and determine the positions of the eight bare chips that make up the upper and lower bridge arm switches.
C. The effect of threshold voltage difference between parallel chips on temperature imbalance
The test voltage and current were 400V bus voltage and 200Hz 340 Arms sinusoidal phase current, respectively. The thermal imbalance phenomenon at different power dissipation was tested using two switching frequencies of 8kHz and 12kHz [3].
The purpose of temperature measurement is to quantify the temperature difference between the highest and lowest temperature chips among the 32 chips in the full bridge, and to compare the heat dissipation performance of the GAP 1 module and the GAP 2 module under the same switching frequency conditions.
It is worth mentioning that, to ensure the experimental setup met the required measurement accuracy, a pre-characterization measurement process was performed on the FLIR E-76 thermal imager. Key parameters involved included the mounting angle and the emissivity related to the surface material and external lighting conditions. Calibration was performed by heating the power module with a hot plate within a steady-state temperature range of 50°C to 175°C. Finally, the NTC readings were checked against the hot plate temperature setpoint to ensure consistency.
Thermal imaging only began after the experimental setup was calibrated. Figures 8 and 9 show infrared thermal images of the GAP 1 module at a switching frequency of 12 kHz, along with the junction temperature measurements of each chip within the switch.
The image below is an infrared thermal image of bridge arm W at a switching frequency of 12 kHz.
The same temperature measurement experiment was performed on the GAP2 module. The eight bare chips at the top of the diagram belong to the upper bridge arm switches, while the eight bare chips at the bottom belong to the lower bridge arm switches. Temperature analyses were performed on the GAP1 and GAP2 modules at switching frequencies of 8kHz and 12kHz, respectively. The table below summarizes the measurement and analysis results, reporting the maximum and minimum temperatures measured at each step.
Table 2: Test Results
In the GAP 1 module, the temperature difference between the highest and lowest temperature chips is 4.4 °C at 8 kHz and 4.6 °C at 12 kHz. In the GAP 2 module, where Vth is selected according to the selection criteria, the thermal increment is 6.3 °C at 8 kHz and 8.7 °C at 12 kHz.
D. Conclusion
Tests show that reducing the threshold voltage difference of parallel silicon carbide chips can significantly reduce the temperature difference between the chips. Furthermore, as the switching frequency increases, the method of reducing temperature difference by decreasing the die threshold voltage difference becomes more effective; specifically, in the tests, the temperature difference was reduced by 25% at 8 kHz and by nearly 50% at a switching frequency of 12 kHz. Factors contributing to switching power dissipation include Eon, Eoff, and diode reverse recovery losses, as well as the switching frequency.
Experimental results show that, for given selection criteria, increasing the switching frequency to reduce temperature difference is in no way as effective as reducing the threshold voltage distribution range. Due to numerous technical challenges during measurement, including bus overheating and power supply voltage ripple, testing could not be performed at the typical nominal battery voltage of previous-generation electric vehicles. This is expected to widen the temperature difference; therefore, starting with selection criteria or device threshold voltage ranges, mathematical models that can predict junction temperature imbalances would be extremely helpful.
