1 Introduction With the development of modern technology, semiconductor devices and components have been widely used in engineering and commerce. Its extensive applications in radar, remote control and telemetry, aerospace and other fields have put forward increasingly higher requirements for its reliability. The failure caused by poor chip soldering (bonding) has also attracted more and more attention, because such failure is often fatal and irreversible. There are many methods for soldering (bonding) chips to packages, which can be summarized into two categories: metal alloy soldering (or low melting point soldering) and resin bonding [1]. Their chip connection mechanisms are very different, and they must be rationally selected according to the type and requirements of the device. In order to obtain ideal connection quality, it is also necessary to analyze the mechanism and characteristics of various soldering (bonding) methods in a targeted manner, analyze the many factors affecting their reliability, and continuously improve them in the process. This paper briefly describes the mechanism of the two major categories of semiconductor device soldering (bonding) methods, compares the characteristics and applicability of several commonly used methods, and discusses the failure mode of gold-silicon alloy soldering, which is the most widely used in semiconductor devices, and its solution. 2. Chip Soldering (Attachment) Methods and Mechanisms Chip soldering refers to the method of forming a strong, conductive, or insulating connection between a semiconductor chip and its carrier (package housing or substrate). In addition to providing mechanical and electrical connections, the solder layer must also provide a good heat dissipation channel for the device. Methods can be divided into resin bonding and metal alloy soldering. Resin bonding uses a resin adhesive to form an insulating layer between the chip and the package, or to dope it with metals (such as gold or silver) to form a good conductor of electricity and heat. Epoxy resin is most commonly used as the adhesive. Epoxy resin is a stable linear polymer. After the addition of a curing agent, the epoxy groups open to form hydroxyl groups and cross-link, thus forming a network structure from the linear polymer and curing it into a thermosetting plastic. The process progresses from liquid or viscous liquid → gelation → solid. The curing conditions are mainly determined by the type of curing agent. The content of the doped metal determines its electrical and thermal conductivity. Silver-doped epoxy bonding is one of the most popular chip bonding methods currently. It requires a low curing temperature, which can avoid thermal stress, but it has the disadvantage of silver migration [2]. In recent years, gold conductive adhesives used in small and medium power transistors have been superior to silver conductive adhesives [3]. Non-conductive fillers include alumina, beryllium oxide and magnesium oxide, which can be used to improve thermal conductivity. Resin bonding is widely used because the carrier does not need to be heated during the operation, the equipment is simple, the process is easy to automate, and it is economical. It is especially widely used in integrated circuits and small power devices. Resin-bonded devices have high thermal resistance and electrical resistance. Resin is easy to decompose at high temperatures, and filler precipitation may occur, leaving only a layer of resin on the bonding surface, which increases the resistance at that point. Therefore, it is not suitable for devices that require high temperature operation or low bonding resistance. In addition, the mechanical strength of the bonding surface of resin bonding is far less than that of eutectic bonding. Metal alloy bonding mainly refers to eutectic bonding of gold silicon, gold germanium, gold tin, etc. Here, gold silicon eutectic bonding is mainly discussed as an example. Gold has a melting point of 1063℃, and silicon has a melting point of 1414℃, but the melting point of gold-silicon alloys is much lower than that of elemental gold and silicon. As can be seen from the binary phase diagram, the eutectic point temperature of the Au-Si eutectic melt, containing 31% silicon atoms and 69% gold atoms, is 370℃. This eutectic point is the main basis for selecting the appropriate welding temperature and controlling the welding depth. The gold-silicon eutectic welding method involves placing the chip under certain pressure (with friction or ultrasound). When the temperature is above the eutectic temperature, the gold-silicon alloy melts into a liquid Au-Si eutectic melt. After cooling, when the temperature is below the eutectic temperature, the eutectic melt transforms from a liquid phase into a mechanically combined mixture of grains—the gold-silicon eutectic crystal—and solidifies completely, thus forming a strong ohmic contact welding surface. Eutectic welding has advantages such as high mechanical strength, low thermal resistance, good stability, high reliability and less impurities. Therefore, it has been widely used in the chip assembly of microwave power devices and components and is favored by the high reliability device packaging industry. Its welding strength has reached 245MPa[4]. Metal alloy welding also includes "soft solder" welding (such as 95Pb/5Sn, 92.5Pb/5In/2.5Ag). Due to its relatively low mechanical strength, it is not commonly used in semiconductor device chip welding. The following is a comparison of several welding (pasting) methods, as shown in Table 1. Regardless of the welding method used, the sign of success is that the interface between the chip and the package is firm, flat and without voids. Since Au-Si eutectic welding is the most widely used in semiconductor devices and microelectronic circuits, this paper mainly discusses the failure causes and solutions of this welding method in combination with actual work. 3 Failure Mode Analysis 3.1 Poor Ohmic Contact Good ohmic contact between the chip and the substrate is the premise for ensuring the normal operation of power devices. Poor ohmic contact will increase the thermal resistance of the device, cause uneven heat dissipation, affect the current distribution in the device, damage the thermal stability of the device, and even burn out the device. There are three ways of heat dissipation of semiconductor devices: radiation, convection and conduction, among which heat conduction is the main way of heat dissipation. Taking silicon microwave power transistor as an example, Figure 1 is the assembly model of silicon microwave power transistor, and Figure 2 is its thermal equivalent circuit. Tj is the junction temperature of the die, TC is the case temperature; R1, R2, R3, R4 and R5 are the thermal resistances of the chip, Au-Si welding layer, BeO, interface solder layer and tungsten copper base, respectively. Total thermal resistance R = R1 + R2 + R3 + R4 + R5. The heat generated by the collector junction of the chip is mainly transferred to the WCu case through the silicon wafer, welding layer and BeO. The poor soldering and voids of the Au-Si welding layer are the main causes of poor ohmic contact. Voids will cause current density effect, and irreversible and destructive thermoelectric breakdown may be formed near it, that is, secondary breakdown[5]. Poor ohmic contact of the welding layer brings great hidden dangers to the reliability of the device. 3.2 Thermal Stress Failure This is a type of failure caused by mechanical stress. Since its final manifestation is often solder joint cracks or chip peeling, it is discussed here as one of the micro-soldering failure modes. The solder interface of microelectronic devices is composed of materials with varying properties, such as Si, SiO2, BeO, Al2O3, and WCu. These materials have different coefficients of linear thermal expansion; for example, WCu, commonly used as a base, has a coefficient of expansion almost four times greater than that of Si crystal. When they are bonded together, compressive or tensile stress exists between the different material interfaces. Microwave power devices often undergo thermal cycling during operation. Due to the difference in thermal expansion coefficients between the chip and the package, periodic shear stress is generated between the solder joints during thermal cycling. This stress may accumulate at void locations, causing solder cracks or even silicon wafer cracking, ultimately leading to device failure due to thermal fatigue. In the solder layer between the chip and the casing, the maximum thermal shear deformation can be estimated as [6] S=DΔαΔT/2d (1) where D is the diagonal size of the chip; d is the thickness of the solder layer; ΔT=Tmax－Tmin, Tmax is the solidification temperature of the solder, Tmin is the lowest temperature in the device screening; Δα is the difference in thermal expansion coefficient between the chip and the substrate material. As can be seen from the above formula, the thermal deformation is directly proportional to the size of the chip. The larger the chip size, the greater the shear force it will have to withstand in the temperature cycle after welding. From this perspective, it is very necessary for high-power devices to adopt small chip multi-cell synthesis. In welding, the thermal matching between the chip and the substrate must be fully considered. If a ceramic substrate (such as AlN) with a thermal expansion coefficient very close to that of silicon is used in silicon devices, the thermal stress will be greatly reduced and it can be used for large chip assembly. 4 Three inspection methods for welding quality 4.1 Shear force measurement This is the most commonly used and intuitive method for inspecting the welding quality between the chip and the substrate. Figure 3 shows the relationship between the minimum shear force and chip area of ​​GJB548A-96 used to test chip soldering. In cases of good soldering, even if the chip breaks, a large chip residue remains at the solder joint. Generally, chip substrate material does not adhere to solder voids, and the size and density of the voids can be directly observed after the chip is removed. Figure 4 shows a photograph of solder voids observed after a chip in a certain device was removed. For devices bonded using resin bonding, if long-term operation is required at higher and lower temperatures, the shear force intensity at different temperatures should be measured [7]. 4.2 Electrical Performance Testing For bipolar devices with conductive connections between the chip and substrate or base (such as eutectic bonding, conductive adhesive bonding), the quality of the soldering (bonding) directly affects the thermal resistance and saturation voltage drop Vces of the device. Therefore, for devices such as transistors, the soldering quality of the chip can be non-destructively inspected by measuring the device's Vces. If Vces is too large while ensuring good chip electrical performance, it may indicate a poor solder joint or a large "void". This method can be used for online testing in mass production. 4.3 Ultrasonic Testing The theoretical basis of ultrasonic testing is that the interfaces of different media have different acoustic properties and different abilities to reflect ultrasonic waves. When ultrasonic waves encounter a defect, they will be reflected back to produce a "shadow" with a projection area similar to that of the defect. For devices using multilayer metal-ceramic packaging, the back side of the package often needs to be thinned before testing. At the same time, welding failures caused by thermal stress are difficult to detect using general testing and inspection methods. High stress must be applied to the device, and the defects are usually activated after aging, that is, they can only be detected after the device fails. Figure 5 is an ultrasonic scanning photograph of a failed device after back side thinning. The area inside the black circle is the welding defect. Ultrasonic waves can accurately detect the location and size of defects in the welding area. Ultrasonic testing using an ultrasonic flaw detector is an effective method for inspecting the quality of chip welding. 5 Causes of Welding Defects and Corresponding Measures 5.1 Backside Oxidation of Chips In the production process of devices, gold is often evaporated on the back side of the chip before welding. At the Au-Si eutectic temperature, Si will penetrate the gold layer and oxidize to form SiO2. This SiO2 layer will cause uneven welding wetting, resulting in a decrease in welding strength. Even at room temperature, silicon atoms slowly migrate to the gold surface through inter-grain diffusion. Therefore, the shielding gas N2 must have a sufficient flow rate during soldering, and it is best to add some H2 for reduction. Chip storage should also be given sufficient attention, considering not only the ambient temperature and humidity but also its future solderability. Chips not used for a long time should be stored in a nitrogen cabinet. 5.2 Soldering Temperature Too Low Although the Au-Si eutectic point is 370℃, some heat is lost during transfer, so a slightly higher temperature should be chosen, but not too high, to avoid oxidation of the casing surface. The soldering temperature should also be adjusted according to the casing material, size, and heat capacity. To ensure soldering quality, the surface temperature of the heating base should be measured regularly with a surface thermometer, and the temperature of the soldering surface should be monitored when necessary. 5.3 Insufficient or Uneven Pressure During Soldering A certain pressure should be applied to the chip during soldering. Insufficient or uneven pressure will cause gaps or poor soldering between the chip and the substrate. Table 2 compares the shear strength of a certain type of chip under different pressures. As shown in Table 2, the chip shear strength decreased significantly after the pressure was reduced, and the residual area of ​​the silicon wafer was observed to be less than 50% in the experiment. However, the pressure should not be too high to avoid fragmentation. Therefore, the adjustment of the pressure during soldering is very important. It should be adjusted according to the chip material, thickness, and size. Targeted data accumulation in practice is necessary to achieve the ideal soldering effect. 5.4 Poor Substrate Cleanliness Contamination, local oil stains, or oxidation of the substrate will seriously affect the wettability of the soldering surface. This contamination is relatively easy to observe during the soldering process, and the substrate must be reprocessed. 5.5 Excessive Thermal Stress Failure caused by thermal stress is a slow, gradual process that is not easily detected but is extremely harmful. Generally, the greater the chip thickness, the lower the corresponding stress. Therefore, the chip should not be too thin. In addition, if the thermal properties of the substrate or base are not compatible with those of the chip, it will also cause great mechanical stress. Before soldering, the substrate or base can be preheated to 200°C, and the pick-up tip can also be appropriately heated to reduce thermal shock. After soldering, slow cooling under a nitrogen (N2) protective atmosphere can relieve some stress. 5.6 Thin Substrate Gold Layer: When the gold plating on the substrate is thin and not dense enough, even under nitrogen protection, severe discoloration will occur at the Au-Si eutectic temperature, affecting soldering strength. Experiments show that for a 1mm × 1mm chip, a gold plating thickness greater than 2μm is required for reliable eutectic bonding. Generally, the larger the chip size, the greater the gold plating layer needs to be. 6 Conclusion With technological advancements, chip soldering (bonding) methods are becoming increasingly diverse and sophisticated. Semiconductor device soldering (bonding) failures are mainly related to poor surface cleanliness, unevenness, oxide presence, improper heating, and substrate plating quality. Resin bonding methods are also constrained and influenced by the composition and physical and mechanical properties of the adhesive. To solve the problem of poor chip micro-soldering, it is necessary to understand the mechanisms of different methods, analyze various failure modes one by one, identify adverse factors affecting soldering (bonding) quality in a timely manner, strictly inspect the production process, and strengthen process management in order to effectively avoid the potential harm to device reliability caused by poor chip soldering.