Abstract: With the continuous improvement of CCD performance, CCD technology has been widely used in both military and civilian fields. This paper introduces the driving circuit design of TCD1501C linear CCD, and details the CCD image sensor driving timing design and video output differential signal driving circuit design implemented using VHDL. Keywords: Linear CCD; Image sensor; Instrumentation amplifier; Differential drive 1 Introduction Charge-coupled device (CCD) is a new type of semiconductor device that emerged in the late 1960s. Currently, with the continuous improvement of CCD device performance, its application in image sensing, size measurement, and positioning and control is becoming increasingly widespread. The front-end driving circuit of CCD applications is expensive, and its performance is constrained by the technical and process level of manufacturers, causing great inconvenience to users. There are two types of CCD drivers: one type outputs an analog signal from the CCD device under pulse action, which is then amplified by a back-end gain adjustment circuit before being sent to the user; the other type includes a part that digitizes the analog signal according to a certain output format and then transmits the digital information to the user. Linear CCD cameras typically refer to the latter, which, with the addition of a mechanical scanning device, can produce an image. Therefore, selecting different models of linear CCD devices and designing convenient and flexible driving circuits to match them according to different application fields and technical specifications is one of the key technologies in CCD applications. This article takes the TCD1501C CCD image sensor as an example to introduce its performance parameters and the design of its peripheral driving circuit. The driving timing parameters can be flexibly set through VHDL programs. This circuit has been successfully developed and applied to a certain type of non-contact position measurement product. 2 CCD Working Principle CCD uses electric charge as a signal, unlike most other devices that use current or voltage as signals. Its basic functions are the generation, storage, transmission, and detection of signal charge. When light is incident on the photosensitive surface of the CCD, the CCD first completes photoelectric conversion, that is, generates photocharge that is linearly related to the amount of incident light radiation. The working principle of CCD is that the light reflected from the object is onto the CCD device. The CCD accumulates corresponding charges according to the intensity of the light, generating a weak voltage signal proportional to the amount of photocharge. After filtering and amplification, the driving circuit outputs an electrical signal or a standard video signal that can represent the intensity of light on the sensitive object. Based on the principle of converting one-dimensional optical information into electrical information output, linear CCDs can realize image sensing and size measurement functions. Figure 1 shows the CCD spectral response curve. 3. Implementation of the Driving Circuit The main technical specifications of the linear CCD TCD1501C are as follows: 5000 pixel number; pixel size 7 μm x 7 μm; pixel center distance 7 μm; total pixel length 35 mm; spectral response range 400 nm to 1000 nm; peak wavelength 550 nm; sensitivity 10.4 V/lx.s to 15.6 V/lx.s. The driving circuit that enables the CCD chip to work normally has two main functions. First, it generates the multiple timing pulses required for CCD operation; second, it processes the original analog signal output by the CCD, including gain amplification, differential signal to single-ended signal conversion, and finally, the driver outputs the analog or video information required by the user. 3.1 VHDL-based Driving Timing Design This section describes a design based on Xilinx's CPLD-XC9572-PC44-10, implemented in the ISE 6.1 environment. CCD devices require complex three-phase or four-phase overlapping driving pulses. Most area CCDs are driven by three-phase or four-phase pulses, while most linear CCDs are driven by two-phase pulses. This paper takes the two-phase linear CCD image sensor TCD1501C as an example to implement the driving circuit design using a CPLD. CCDs are capacitive loads and consume power at high operating frequencies. Therefore, the reset pulse RS, shift pulse (also known as optical integration pulse) SH, clamping pulse CP, sampling and preservation pulse SP, and two-phase clock pulses φ1E and φ2E output by the CPLD need to be shaped and amplified using a 74HCl4 filter before being sent to the corresponding input terminals of the TCD1501C device. The analog signal output of the CCD will then yield the signal OS and the compensation signal DOS. The typical optimal operating frequency of the TCD1501C is 1MHz, and this device has 5,000 effective pixel outputs. For normal operation, the TCD1501C requires 76 dummy pixel outputs, and at least 5,076 clock pulses should be included within one scan line cycle, i.e., TSH > 5,076 x φ1E 0.1μs. In this design, TSH = 5200 x φ1E. Therefore, changing the clock pulse frequency or increasing the number of clock pulses within the optical integration pulse period can alter the optical integration period. Typically, the frequency of φ1E is set to be adjustable, allowing for flexible use of the CCD device's advantages to modify the optical integration time according to the actual application environment. Whenever possible, the frequency of the CCD drive pulse should be as low as possible to reduce the charge transfer loss rate of the CCD. When the drive pulse frequency is reduced, a significant increase in the amplitude of the CCD output signal can be observed on an oscilloscope. Figure 2 shows the CCD operating waveform. Below is the VHDL program for generating timing pulses: 3.2 Differential Drive Design of CCD Output Signal Based on AD623 Under the action of the drive pulse, the CCD sequentially outputs video signals through a shift register. Each time the reset pulse RS resets, the CCD outputs a light pulse signal. Because the TCD1501C signal detection uses a gating charge integrator structure, some crosstalk signals caused by the periodic reset signal RS are superimposed in its video output signal. Moreover, the effective signal amplitude is small, about 500 mV, and the DC voltage is about 4.1V. This is a typical differential signal with a high common-mode voltage and a low effective differential-mode signal. The signal waveforms are shown in Figures 3 and 4. Therefore, before the analog signal output is processed (including long-distance transmission, A/D conversion, etc.), a series of preprocessing steps are required to eliminate reset pulse crosstalk and other interference in the video signal, and to amplify the amplitude and drive capability of the weak video signal. Since this is the processing of differential signals, the basic concepts of differential circuits will be discussed first. Figure 5 shows a schematic diagram of differential and common-mode voltages in a differential signal measurement circuit. VDIFF is the differential-mode voltage, VCM is the common-mode voltage, and the signal output VOUT = R2/R1·VDIFF = G·VDIFF. Ideally, the differential-mode gain G ≥ 1, while the common-mode gain (%mismatch/100) x G/(G+1) is close to zero. Therefore, it can be seen that the common-mode gain is mainly a function of resistor mismatch. In actual measurement circuits, a small mismatch in resistor values ​​may cause the common-mode voltages at the two input terminals to be inconsistent, resulting in a non-zero DC common-mode gain. The common-mode rejection ratio (CMRR) is the ratio of the differential-mode gain G to the common-mode gain, expressed in logarithmic form as: 20lg [(100/%mismatch) × (C+1)]. In practical engineering applications, circuits operate within a large noise source, such as 50 Hz AC power line noise, equipment switching noise, and wireless signal transmission noise. These interference signals, acting on the differential input, will generate a common-mode signal at the output. Therefore, differential signal processing requires not only high DC CMRR but also high AC CMRR. In this circuit design, the Analog Devices (ADI) instrumentation amplifier AD623 was selected, and its internal structure is shown in Figure 6. The AD623 integrates three operational amplifiers, can operate with single or dual power supplies, and features high CMRR and extremely low voltage drift. Except for an external resistor controlling the programmable gain, all components are integrated internally, improving circuit temperature stability and reliability. The CCD analog signal processing circuit using the AD623 is shown in Figure 7. The video signal and its compensated output are sent to the inverting and non-inverting inputs of the AD623, respectively. An emitter follower is connected to the output of the AD623 to enhance the signal driving capability. Using this device eliminates the temperature drift of the output signal caused by using ordinary operational amplifiers and external resistors. 4. Conclusion The linear CCD driver developed above has been successfully debugged and is used in a position measurement system, operating stably and reliably. This design scheme can be applied to the front end of an imaging system by further expanding the AD conversion section.