The ADC16DV160 is a monolithic, dual-channel, high-performance CMOS analog-to-digital converter (ADC) capable of converting analog input signals to 16-bit digital words at a rate of 160 megasamples per second (MSPS). This converter employs a differential, pipelined architecture with digital error correction and on-chip sample-and-hold circuitry to minimize power consumption and external component count while providing excellent dynamic performance. Automatic power-on calibration enables superior dynamic performance, reduces component-to-component variations, and the ADC16DV160 can be recalibrated at any time via a 3-wire Serial Peripheral Interface (SPI). Integrated low-noise, stable voltage reference and differential reference buffer amplifiers simplify board-level design. An on-chip duty cycle stabilizer with low added jitter allows for a wide range of input clock duty cycles without compromising dynamic performance. A unique sample-and-hold stage generates a full-power bandwidth of 1.4 GHz. The interface between the ADC16DV160 and the receiver block can be easily verified and optimized via fixed-pattern generation and output clock positioning functions. Digital data is provided via dual data rate LVDS outputs – enabling a 68-pin 10mm x 10mm VQFN package. The ADC16DV160 operates on dual +1.8V and +3.0V supplies and features power-down functionality to reduce power consumption to extremely low levels while allowing for rapid recovery to full operating status.
Because ADCs are very expensive, and repairing damaged equipment is even more costly, it is crucial to ensure that this voltage level is not exceeded. This means that the preamplifier stage must be designed to never exceed this voltage.
Here, we will discuss how to protect the ADC.
For this example, we will continue to use the ADC16DV160. The ADC input common-mode voltage is 1.15V ± 0.05V. The maximum (linear) input signal is 2.4-Vpp differential. The 2.4-Vpp differential signal is 1.2-Vpp on each input. Under normal operating conditions, the swing of each pin is no less than 1.15-V – 0.05-V – 0.6-V = 0.5-V. Similarly, the upper limit of the swing is 1.15-V + 0.05-V + 0.6-V = 1.8-V. The absolute maximum voltage of 2.35V differs from the normal operating range by only 0.55V.
Furthermore, the ADC16DV160 has an SFDR (spurious-free dynamic range) of 98dB and an input tone of -1dBFS. To maintain this linearity, the ADC driver needs a P1dB point of 18dBm or higher. Under 200 Ohm input load conditions and 6dB matching losses, the ADC driver can provide approximately 5Vpp at the ADC input. This means the ADC driver can produce a positive swing of 2.45V, which exceeds the ADC's absolute maximum voltage and risks damaging the ADC.
One way to solve this problem is to use an amplifier with output clamping, such as the LMH6553, because it has an output clamping accuracy of 40m-V and a recovery time of 600ps. The LMH6553's output clamping is set to 2.1V and it can still easily pass full-scale ADC signals. With 40mV accuracy, it can also clamp well up to the absolute maximum voltage of 2.35V.
The following diagram helps illustrate the input signal of the ADC. A normal input signal is shown, where the ADC is operating in the linear region. A key point is that the differential signal consists of two single-ended signals with opposite phases. One of the single-ended signals, representing the actual voltage supplied to the ADC pin, is shown. The diagram also includes the differential input and output signals, and is mathematically centered on the graph, even though each signal has a positive common-mode voltage.
Overdrive input: Demonstrates how to protect the ADC through clamping action.
Analog systems requiring high speed, low distortion, and voltage clamping can benefit from clamping amplifiers like the LMH6553. Using a clamping amplifier can protect sensitive and expensive high-performance ADCs.
The LMH6553 is a 900 MHz differential amplifier with an integrated adjustable output limiting clamp. The clamp enhances system performance and provides transient overvoltage protection for subsequent stages. The LMH6553's internal clamping characteristics reduce or eliminate the need for external discrete overload protection networks. When used to drive an ADC, the amplifier's output clamping allows protection of low-voltage ADC inputs from overdriving and damage by large input signals appearing at the system input. A fast 600 ps overspeed recovery ensures that the amplifier output recovers quickly from a clamping event and rapidly follows the input signal. The LMH6553 offers exceptional bandwidth, distortion, and noise performance, ideal for driving ADCs up to 14 bits. The LMH6553 is also suitable for automotive, communications, medical, test and measurement, video, and LiDAR applications.
With an external gain setting resistor and integrated common-mode feedback, the LMH6553 can be configured as a differential input with differential output or a single-ended input with a differential output gain block. The LMH6553 can be AC or DC coupled at its input, making it suitable for a wide range of applications, including communication systems and high-speed oscilloscope front-ends. Available in 8-pin SO PowerPAD and 8-pin WSON packages, the LMH6553 is part of our LMH family of high-speed amplifiers.
