1. Introduction CAN (Controller Area Network) bus is a serial communication network that effectively supports distributed or real-time control, and is a type of fieldbus. CAN bus has advantages such as high communication speed, good openness, strong error correction capability, and low system cost, and is now widely used in various fields such as mechanical industry, robotics, and medical devices. However, due to the limitations of CAN transceivers, a CAN bus network can only have a maximum of 110 CAN nodes and a maximum communication distance of 10 km. Therefore, when the required CAN bus network size exceeds these limitations, it is necessary to expand the CAN bus network. Currently, the common expansion method is to add CAN bus repeaters. The main task of a CAN repeater is to forward data between two CAN network segments. It has advantages such as filtering traffic, extending communication distance, increasing the maximum number of nodes, allowing different communication speeds for different network segments, improving reliability, and improving network performance. It is one of the key devices in CAN networking. Repeaters are frequently used in slightly larger CAN bus networks. Typically, CAN repeaters are implemented based on two independent CAN controllers. While such CAN repeaters can extend communication distance and increase the maximum number of nodes, their data storage and forwarding rely on the CPU's internal cache, leading to excessive data interaction between the CPU and the CAN controller. This increases communication system latency, degrades real-time performance, and burdens the CPU. Furthermore, under heavy network loads, the limited capacity of the CPU's internal cache can cause frame loss, reducing system reliability. However, real-time performance and reliability are crucial for communication systems. To address the shortcomings of these repeaters in terms of real-time performance and reliability, we design a CAN repeater using an independent dual-CAN controller as the controller for two CAN interfaces. Utilizing the built-in FIFO and gateway features of the independent dual-CAN controller, the two CAN nodes share the resources of the dual-CAN module, allowing direct data exchange between the two individual CAN nodes via the FIFO without using the CPU's internal cache. This reduces data interaction between the CPU and the controller, optimizes CAN bus transmission, significantly reduces CPU load, and improves the overall system's real-time performance and reliability. 2. Introduction to the Independent Dual-CAN Controller The independent dual-CAN controller consists of two full-CAN functional nodes. However, it is not simply a combination of these two CAN nodes; rather, these two can be used independently, or, through the gateway function of the dual CAN controller, a repeater device can be designed that significantly reduces the CPU load. In addition, the dual CAN controller also features power-saving functions, more interrupt functions, and enhanced filtering functions. Its information exchange channel with the microcontroller offers both serial and parallel options. Figure 1 shows the structural block diagram of the independent dual CAN controller. It consists of CAN nodes A/B, a message object buffer, a dual CAN control module, port control, a bus interface, and interrupt control modules. The port control module enables CAN nodes A/B to transmit and receive data; the bus interface module receives information from the CPU, such as chip select, clock, address, and read/write signals, enabling information interaction with the CPU; the interrupt control module is responsible for organizing interrupt source information and sending interrupt signals to the CPU; the dual CAN control module is a global control interface, including initialization logic, global control and status logic, and an interrupt request receiver; the message buffer unit contains a message buffer, FIFO buffer management, gateway control logic, and a message based on the interrupt request generation unit. CAN nodes A and B each include a bit stream processor, a bit timing control unit, error handling logic, an interrupt request generation unit, and node control logic. The CAN nodes A and B, message object buffer, and dual CAN control module constitute the core of the independent dual CAN controller. Figure 2 shows the detailed structure of these core modules. 3. Repeater Design Based on Independent Dual CAN Controller The independent dual CAN controller supports automatic information transmission between two separate CAN buses. Its gateway function is implemented through a shared CAN message object memory between the two separate CAN nodes, allowing message forwarding without CPU intervention. By setting the CAN node selection bit of the message object in the message configuration register, each message object stored in the message memory is associated with either node A or node B. Information exchange between the two nodes can be achieved by connecting two message objects (normal gateway mode) or by sharing a common message object (shared gateway mode). This paper designs a CAN repeater using the shared gateway mode. The designed repeater can automatically send continuously transmitted data frames from the data source connected to it by CAN node A to the target CAN bus via CAN node B, and vice versa. 3.1 Hardware Design of the CAN Repeater The CAN repeater mainly consists of a microcontroller and two CAN controller interfaces. Currently, the microcontroller (CPU) of this repeater is an 89C52, which is responsible for the monitoring of the entire repeater. The two CAN controller interfaces use independent dual CAN controllers (82C900), optocoupler circuits, and CAN bus drivers (82C250). Both CAN bus drivers use isolated DC/DC modules for separate power supply. This not only achieves electrical isolation between the two CAN interfaces but also isolation between the CAN repeater and the bus. Isolation measures can limit faults to a specific network segment, preventing them from affecting other segments, thus facilitating maintenance and ensuring system security. Figure 3 shows the hardware structure of the CAN repeater. In addition to the above components, the hardware of this CAN repeater also includes LED indicators, E2PROM, and a watchdog timer. A total of seven LEDs are used: one for power-on indication, four for receiving and transmitting on the two CAN interfaces, and two for communication fault indication on the two CAN interfaces. These LED indicators provide a basic understanding of the current operating status of the entire system. The reset circuit design employs three reset methods: power-on reset, manual reset, and software reset. Upon power-on, the 89C52 and 82C900 microcontrollers can be reset; alternatively, a manual switch can force a reset. Software reset is primarily controlled by a watchdog timer (MAX1232). When the software enters an infinite loop, the watchdog sends a reset signal to reset the system, ensuring smooth software operation. This design facilitates debugging and troubleshooting problems that arise during system operation. The E2PROM uses a 1 kB 24LC08 chip, used to store CAN repeater configuration parameters and other information for flexible system configuration. 3.2 CAN Repeater Software Design Figure 4 illustrates the operating state of the independent dual CAN controllers in this repeater. The node receiving data frames is the source, while the node transmitting data frames through the repeater is the destination. A shared message object is set as the receiving object of the source. When the data frame send bit GDFS is set to 1 (i.e., the corresponding data frame is automatically sent), it receives a data frame. By inverting the message object node selection bit NODE (0 indicates that the message object is assigned to CAN node A, 1 indicates that the node is assigned to CAN node B) and the message object direction control bit DIR (0 for receiving object, 1 for sending object), the message object send request bit is set, and the message object becomes a sending object of the target, simultaneously sending the relevant data frame without any CPU intervention. After the message object is successfully sent, the message object send request bit is reset, and the shared message object returns to its initial function as a receiving object associated with the source. For the CPU, due to the time requirements of communication, the software design aims to minimize the data forwarding time; therefore, the CPU uses interrupt mode when receiving data. The software design of the CAN repeater mainly includes the following parts: initialization program, main monitoring program, repeater function interrupt subroutine, etc. In the initialization program, the 89C52 initialization performs initial settings for the chip's I/O and stack to ensure normal operation; the dual CAN controller initialization mainly refers to setting the mode, bus timing, interrupt enable, mask code, and ID number, which are implemented by configuring the internal registers of the 82C900 chip. The main monitoring program is responsible for monitoring the entire system and calling the corresponding interrupt service routine when an interrupt is detected. When the main monitoring program receives an interruption in the receive message of a certain node, it calls the repeater function interrupt subroutine. The repeater function interrupt subroutine implements the message receiving and forwarding process shown in Figure 4, realizing the repeater function. Figure 5 is the software program flowchart of the CAN bus repeater. 3.3 Performance Comparison of Two Types of CAN Repeaters When performing store-and-forward, the CAN repeater based on two independent CAN controllers first reads the data frame received by one CAN node from its controller FIFO and stores it in the CPU's internal cache, and then the CPU's internal cache writes the data frame to the FIFO of the other CAN node controller and sends it. CAN repeaters based on independent dual CAN controllers utilize the unique gateway function of these controllers and the shared FIFO feature of their two CAN nodes. Therefore, during operation, by configuring the values ​​of the corresponding registers in the dual CAN controllers (such as the message configuration register and the gateway control register for the message object), data frames received by one node can be stored in the shared FIFO, and then read directly from the shared FIFO and sent by the other node. Since messages do not need to be relayed through the CPU's internal memory, the data interaction between the CPU and the controller is significantly less in CAN repeaters using independent dual CAN controllers than in CAN repeaters based on two independent CAN controllers. This minimizes data storage and forwarding time, reduces communication latency, and improves system real-time performance. Furthermore, because CAN repeaters based on independent dual CAN controllers do not use the CPU's internal memory for store-and-forward operations, they avoid frame loss caused by limited CPU internal memory during heavy communication tasks, greatly improving system reliability. Through the above analysis, we can see that CAN repeaters based on independent dual CAN controllers outperform CAN repeaters based on two independent CAN controllers in both real-time performance and reliability. 4. Conclusion The CAN repeater based on independent dual CAN controllers avoids the limitations of CPU internal memory space by utilizing the built-in FIFO and gateway functions of the dual CAN controllers, minimizing the CPU's burden on message processing, reducing communication latency, and improving the real-time performance and reliability of the communication system. Practice has proven that this repeater exhibits stable performance and significantly improved real-time performance and reliability. However, its software design is relatively complex, and it is hoped that better software algorithms can be found in the future.