Abstract: In today's high-speed digital system design, the importance of power integrity is increasingly prominent. Among these, the correct use of capacitors is key to ensuring power integrity. This paper addresses the filtering characteristics of bypass capacitors and the differences between ideal and actual capacitors, proposing some suggestions for bypass capacitor selection. Based on this, the paper discusses the generation mechanism of power supply disturbances and ground bounce noise, and provides solutions for bypass capacitor placement, which have certain engineering application value. Keywords: Bypass capacitor; Insertion loss; Current loop; Ground bounce noise 1. Introduction With the reduction in system size, the increase in operating frequency, and the increasing complexity of system functions, multiple different embedded functional modules need to work simultaneously. Only when each module has good EMC and low EMI can the realization of the entire system function be guaranteed. This requires the system itself to not only have good shielding performance against external interference, but also to not generate serious EMI when working simultaneously with other systems. Furthermore, the application of switching power supplies in high-speed digital system design is becoming increasingly widespread, and a single system often requires multiple power supplies. Not only are power supply systems susceptible to interference, but the noise generated during power supply can also cause serious EMC problems for the entire system. Therefore, in high-speed PCB design, better filtering of power supply noise is key to ensuring good power integrity. This article analyzes the filtering characteristics of capacitors, the impact of parasitic inductance on the filtering performance of capacitors, and the current loop phenomenon in PCBs, and then summarizes some points on how to select bypass capacitors. This article also focuses on analyzing the generation mechanism of power supply noise and ground bounce noise, and on this basis, analyzes and compares various placement methods of bypass capacitors in PCBs. 2. Insertion Loss Characteristics, Frequency Response Characteristics, and Filtering Characteristics of Capacitors 2.1 Insertion Loss Characteristics of Ideal Capacitors The ability of EMI power filters to suppress interference noise is usually measured by the insertion loss characteristic. The insertion loss is defined as the ratio of the noise power P1 transmitted from the noise source to the load without a filter and the noise power P2 transmitted from the noise source to the load after a filter is connected, expressed in dB (decibels). Figure 1 shows the insertion loss characteristics of an ideal capacitor. It can be seen that the slope of the insertion loss curve corresponding to a 1μF capacitor is close to 20dB/10 octave. Observing a specific insertion loss characteristic, the insertion loss of the capacitor increases with frequency, meaning the P1/P2 ratio increases. This indicates that after the system is filtered by the capacitor, the noise transmitted to the load is reduced, and the capacitor's ability to filter high-frequency noise is enhanced. Analyzing the formula for an ideal capacitor, when the capacitance is constant, the higher the signal frequency, the lower the loop impedance, meaning the capacitor is better at filtering high-frequency components. The conclusions drawn from both aspects are the same. Further observing the curves corresponding to different capacitors, at very low frequencies, the insertion loss values ​​corresponding to various capacitors are approximately the same. However, as the frequency increases, the insertion loss of smaller capacitors increases more slowly than that of larger capacitors, and the P1/P2 ratio increases more slowly. This means that larger capacitors are better at filtering low-frequency noise. Therefore, when designing high-speed circuit boards, we typically place a 1–10 μF capacitor at the power input terminal to filter low-frequency noise; and a 0.01–0.1 μF capacitor between the power and ground lines of each component on the circuit board to filter high-frequency noise. The impedance of a capacitor connected between the power supply and ground can be calculated using the following formula: The purpose of capacitor filtering is to filter out the AC components superimposed on the power supply system. From the formula above, it can be seen that when the frequency is constant, the larger the capacitance value, the smaller the impedance in the circuit. This makes it easier for AC signals to flow through the capacitor to the ground plane. In other words, it seems that a larger capacitance value results in better filtering. However, this is not the case because actual capacitors do not possess all the characteristics of an ideal capacitor. Actual capacitors have parasitic components, which are formed during the construction of the capacitor plates and leads. These parasitic components can be equivalent to resistance and inductance connected in series with the capacitor, commonly referred to as equivalent series resistance (ESR) and equivalent series inductance (ESL), as shown in the left half of Figure 2. If the parasitic resistance of the capacitor is ignored, the model can be equivalent to the right half of Figure 2. Thus, the capacitor is actually a series resonant circuit. In actual circuit or PCB design, the presence of parasitic inductance will greatly affect the filtering performance of the capacitor. Therefore, capacitors with relatively small parasitic inductance should be selected during system design. 2.2 High-Frequency Response Characteristics of a Real Capacitor As we know from Section 2.1, a real capacitor, due to its parasitic inductance, forms a series resonant circuit during operation. The resonant frequency is given by the formula: where L is the equivalent inductance and C is the actual capacitance. As shown in Figure 3, when the frequency is less than f0, it behaves as a capacitor; when the frequency is greater than f0, it behaves as an inductor. Therefore, a capacitor is more like a band-stop filter than a low-pass filter. The ESL and ESR of a capacitor are determined by its construction and the dielectric material used, and are independent of its capacitance. High-frequency suppression capability is not enhanced by replacing the capacitor with a larger capacitance of the same type. The impedance of a larger capacitance capacitor of the same type is lower than that of a smaller capacitance capacitor when the frequency is below f0; however, when the frequency is greater than f0, the ESL determines that there is no difference in impedance between the two. Therefore, to improve high-frequency filtering characteristics, a capacitor with a lower ESL must be used. The effective frequency range of any capacitor is limited. Since a system contains both low-frequency and high-frequency noise, different types of capacitors are usually connected in parallel to achieve a wider effective frequency range. 3. Analyzing Circulating Current Problems in PCBs Using Capacitor Models Improper placement of power decoupling capacitors can create large current loops on the printed circuit board. To reduce noise, a crucial principle in high-speed PCB design is to minimize the area of ​​signal current loops. In the past, we were accustomed to considering only the outflow, path, and destination of current, rarely considering the return path. In high-frequency circuits, power and ground are generally considered equivalent; therefore, the outflow and return paths of current will form a current loop. Within these current loops, due to various reasons, such as the parasitic inductance of capacitors and the inherent inductance of PCB traces, the loop impedance is not zero. This creates a potential difference when current flows through this loop. If the current is variable, this will generate radiation, interfering with the system. To filter power supplies, bypass capacitors are often added between the power supply and ground in circuit design. Adding bypass capacitors in the loop serves two main purposes: first, it increases the loop's charge storage capacity to prevent excessive instantaneous current and ground bounce noise; second, proper placement of the bypass capacitor provides a nearby ground loop for noise signals, reducing the current loop area and thus reducing loop inductance. Even with bypass capacitors, the noise to be filtered is usually a high-frequency AC signal, so such a loop will still radiate externally. To reduce this radiation, we need to minimize the loop impedance, which requires proper placement of the bypass capacitors. Figure 4 shows a large current loop caused by improper placement of the filter capacitor. Figure 5 is a model of the current loop. From the current loop model, we can see that parasitic inductance exists in the loop. At high frequencies, this manifests as loop impedance, causing power supply spikes and radiating electromagnetic waves that interfere with other parts of the system. In the loop, Ll is the package inductance of the capacitor pin lead; Lpc is the parasitic inductance of the PCB transmission line between the capacitor pin and the device's power or ground pin; and Lic is the parasitic inductance of the device pin lead. Additionally, as discussed earlier, the capacitor itself also has parasitic inductance ESL. Therefore, the total inductance of the loop is: L = 2Ll + 2Lpc + 2Lic + ESL. Since the parasitic inductance of the loop will introduce electromagnetic interference into the entire system, generating voltage spikes, there is a certain relationship between this voltage spike peak and the series inductance. An approximate calculation formula is as follows: Here, V is the maximum noise voltage spike peak, Δt is the transient duration, and ΔI is the device transient current. The values ​​of Δt and ΔI can be found in the device datasheet. For example, the typical transient current Icc of a 74HC is 20mA, and the time required for the output signal to rise from zero to Icc or fall from Icc to zero is 4ns. If we now try to control the inductive noise spike to within 100mV, then we can calculate from the above formula that the maximum value of the series inductance L should not exceed 20nH. In PCB design, designers can reduce loop inductance in the following ways: select capacitors with smaller parasitic inductance to reduce ESL (parasitic inductance values ​​for different capacitor models are shown in Table 1); use surface-mount capacitors as much as possible to reduce capacitor lead length and reduce Ll value; place capacitors appropriately, using power planes or ground planes instead of power or ground transmission lines to reduce power/ground transmission line inductance Lpc; and choose appropriate integrated device packages to reduce Lic value. For example, for the ADV478 device, the parasitic inductance of the PLCC package is 2nH to 3nH smaller than that of the DIP package. 4. Generation Mechanism of Power Supply Disturbance and Ground Bounce Noise Figure 6 shows a simple totem-pole I/O circuit driving a series-source-matched transmission line. In the figure, LV and LG are the packaged inductors for the device's power and ground pins, respectively, and A and B are two field-effect transistors used as switches. Assuming that the voltage and current at all points on the transmission line are initially zero, at a certain moment the device will drive the transmission line to a high level, at which point the device needs to draw current from the power pin. At time t1, switch A is closed, and current flows from VCC on the PCB, through the packaged inductor LV, across switch A, through the series terminating resistor, and then into the transmission line, with an output current amplitude of (1/2)VCC/Z0. The current continues on the transmission line network for a complete round-trip time, ending at time t2. From this point onward, the entire transmission line is fully charged and does not require additional current to maintain its state. When current surges instantaneously through the packaged inductor LV, it will cause a disturbance in the chip voltage at node V1. At time t3, closing switch A does not generate impulse noise because no current flows when switch A is opened. Simultaneously, closing switch B creates a loop consisting of the transmission line, ground plane, package inductor LG, and switch B, resulting in a momentary current flow through switch B and causing ground bounce at node G1. Adding a bypass capacitor (placed inside the chip) between V1 and G1 makes the transient voltage disturbances at V1 and G1 identical. This means that voltage disturbances will occur at both V1 and G1 with each switch switching, but the amplitude will be halved. In high-speed PCB design, placing filter capacitors near power pins is to eliminate power supply disturbances and ground bounce noise. Adding a bypass capacitor increases the total inductance of the loop due to the parasitic inductance of the capacitor, potentially leading to greater noise intensity. Therefore, designers should choose bypass capacitors with low parasitic inductance and place them appropriately on the PCB. 5. Placement of Bypass Capacitors for Device Power Supply Pins When current instantaneously flows into the device through its power supply pin or to ground through its ground pin, power supply disturbances and ground bounce noise will be generated due to the inductance of the device package and the inductance in the power supply loop. Therefore, filter capacitors need to be placed near the power supply pins to eliminate power supply disturbances and ground bounce noise. As mentioned above, power supply disturbances and ground bounce noise mainly originate from the chip pins. Since the output impedance of the chip (the output impedance of the chip's power or ground pins) is generally much larger than the impedance of the power plane or ground plane (otherwise, a large amount of power and ground noise would be generated), the chip can be regarded as a noise source. For a well-designed circuit board, whenever the impedance of the noise source is much larger than the load, the noise source can be regarded as a current source, which will inject a certain amount of current into the power or ground system. To reduce power or ground noise, measures need to be taken to reduce the amount of current injected into the power or ground plane. To achieve this, theoretically, an impedance needs to be connected in series with the power or ground pin. This impedance must be large enough, ideally larger than the output impedance of the chip's power or ground pin. However, connecting such a large impedance in series is impractical because it would generate greater ground bounce noise or power supply disturbances inside the chip, causing it to malfunction. Therefore, the correct approach is to guide the noise to the ground plane through a low-impedance loop. A common practice is to add a bypass capacitor to the chip's power pin. The following is a simple analysis of four capacitor placement methods. Figures 7 and 8(a) show one method of bypass capacitor placement. The chip's ground pin is directly connected to the ground plane through a low-impedance via D (the parasitic inductance of a via is typically 1-2 nH). This allows ground bounce noise on the chip's ground pin to flow into the ground plane through the via, suppressing the impact of ground bounce noise on the chip. The chip's power pin is connected to the capacitor's power pad via a short transmission line (typically 50-80 mil long, with a parasitic inductance of 1-1.6 nH). The capacitor's power pad and ground pad are directly connected to the power plane and ground plane via vias. This creates a low-impedance path between the power pin and the ground plane, effectively mitigating the impact of power supply noise on the chip. Simultaneously, noise on the power plane near the bypass capacitor flows into the ground plane through a low-impedance path via via B, the bypass capacitor, and via C. This placement effectively suppresses noise impact on the chip, power supply, and other systems. As shown in Figure 8(b), via B is placed between the capacitor's power pin and the chip's power pin, increasing the loop inductance of path A. This method is generally used when the capacitor and chip are not on the same layer. As shown in Figure 8(c), the power via B at the capacitor's power pin is moved closer to the chip's power pin A. This placement is similar to the second method described above and will increase the loop inductance; this method should be avoided. As shown in Figure 8(d), the transmission line between the capacitor power supply pin and the chip power supply pin is removed, and the chip power supply pin is directly connected to the ground plane through a via. The capacitor power supply pin and the chip power supply pin are connected together through a large power plane. Thus, path A includes two vias, one power plane, and one capacitor, which also increases the loop inductance. Furthermore, noise will have unpredictable effects on the power plane. Additionally, it increases the number of vias, reducing the wiring area on the board. This method should be avoided as much as possible. 6. Conclusion Currently, the board-level frequency of digital systems is increasing, and various EMI problems are becoming more and more serious. The reasonable selection and use of bypass capacitors is a key aspect of eliminating EMI and achieving power integrity. Moreover, with the further development of semiconductor technology, capacitors are also being updated and replaced to meet the requirements of high-speed circuit design. Therefore, issues such as the selection and placement of bypass capacitors need to be continuously and deeply explored. References 1 Bill Slattery and John Wynne. Design and Layout of a Video Graphics System for Reduced EMI. AN-333 Application note,ANALOG DEVICES. 2 Howard Johnson. On Chip Bypassing with Series Terminations. EDN Magazine, April 29, 2004. 3 Howard Johnson and Martin Graham. High-Speed ​​Digital Design, A Handbook of Black Magic.New Jersey: Pearson Education,Inc 4 The datasheet of AV9170, Integrated Circuit Systems. 5 Howard Johnson. Bypass Arrays.