Introduction The open controller architecture originates from the "open" PC (personal computer) technology. Currently, most open motion controllers are PC + motion control card structures. With the increasing performance of MCUs (microcontrollers) and DSPs (digital signal processors), the trend of MCUs and DSPs replacing PCs is becoming increasingly apparent. This embedded, compact structure has a wider range of environmental adaptability than PCs. MCUs, DSPs, and PCs differ significantly; motion control technology in a PC environment cannot be directly transferred to MCU and DSP systems. Therefore, research on motion control technology based on MCU and DSP hardware platforms is essential. [b]Design Goals and Requirements Analysis: Development Direction of Motion Control Systems[/b] Driven by open controller technology, motion control systems are evolving from traditional closed structures towards open, reconfigurable, and networked directions. According to the definition in "Open CNC Systems Part 1: General Principles" (GB/T18759.1-2002), open CNC systems have three levels of openness. The first level is configurable system functions, with open interfaces for the human-machine interface, motion control interfaces of servo drive units, and logic control units. The second level is open system software architecture, topology, and application software interfaces, allowing third-party application software to be installed, run, and interoperable within the system. Furthermore, third-party software modules can replace and expand the system's software modules without altering the topology. The third level is system reconfigurability. However, the detailed content regarding reconfigurability in GB/T 18759.1-2002 has not yet been published. Motion control systems are a core component of CNC systems, and their technological development direction is similar to that of open CNC systems. Modern motion controllers connect three networks: information network, logic control network, and servo control network (interface). Research Topics on Motion Control Technology in MCU and DSP Environments Compared to PCs, MCUs and DSPs utilize Harvard architecture, pipelined technology, very long instruction words (VLEs), multipliers, etc., to improve CPU speed. They also extend on-chip control with forward and backward peripherals and communication interfaces. In this environment, to achieve open, reconfigurable, and networked motion control functions, the following research is necessary: ​​① Research on system architecture to implement complex motion control using a multi-CPU approach; ② Research on real-time operating systems in embedded systems to solve software problems in MCU and DSP controller systems; ③ Research on motion control algorithms in MCU and DSP environments to solve the implementation problem of complex control algorithms under limited resources; ④ Research on software module management and customization techniques to address the application specificity issues of general technical solutions; ⑤ Research on network communication technologies: solving communication problems in servo communication networks, logic control networks, and information networks. Hardware System Design Goals and Structural Requirements The design goal of the hardware platform for motion control technology research based on MCU and DSP is to provide a hardware system environment for the aforementioned research topics. While commercially available motion controllers based on MCUs or DSPs are not uncommon, they only provide users with interfaces to motion control function libraries and are not fully open. Therefore, a hardware research platform for motion controllers must be developed and meet the following requirements: ① Type and Structure Requirements: The CPU selection should be mainstream MCU and DSP chips. The architecture should adopt single-CPU, dual-CPU pipeline modes, and hierarchical structures. The CPUs can work independently or form a pipeline mode. A two-layer structure can also be adopted, with the upper and lower layers handling tasks with different real-time requirements. ② Openness Requirements: Each CPU unit should be equipped with a computer communication interface, such as RS232, PCI, CAN, USB, etc., to facilitate hardware interconnection. ③ Networking Requirements: Equipped with servo unit interfaces, fieldbus interfaces, and Ethernet interfaces. System Design Motion Control System Hardware Structure The basic hardware structure of the motion control system is shown in Figure 1: The controller connects to the human-machine interface and three networks. The connection between the controller and the human-machine interface often uses open industrial fieldbuses such as ModBus; the controller connects to the Internet/Intranet via Ethernet interface to interact with management information systems; the controller communicates with networked PLC workstations via fieldbuses such as CAN, ModBus, and RS485 to handle a large number of I/O operations of the controlled objects; the controller connects to a high-speed servo network to transmit control signals from the servo amplifier, but this solution is technically difficult, and only a few companies have used dedicated high-speed servo communication networks to achieve servo motor networking. Most solutions still use standardized motor interfaces. The interface of a servo motor is as follows: ① 2-channel pulse waveform output, with a phase difference of 90°, or one of them can be used as a direction signal (high or low); ② 1-channel AD output, generally ±10V, with a bit depth of 12 or 16 bits; ③ 2-channel incremental encoder pulse input, one from the servo motor and the other from the actuator terminal; ④ 3-channel digital signal output, including servo enable, forward rotation limit, and reverse rotation limit; ⑤ 4-channel digital signal input. This includes servo ready, left limit, right limit, and zero-position signals; the above interface circuit can also be connected to a stepper motor. The internal hierarchical structure of the motion controller is shown in Figure 2: the upper-level controller handles complex control algorithms and weak real-time tasks, while the lower-level controller handles strong real-time tasks such as interpolation and servo control. Two DSPs form a dual-DSP pipeline module to process complex real-time control tasks in parallel. [b]Hardware Platform Design and Main Chip Selection for Motion Control System Research[/b] The principle for selecting MCU and DSP chips is applicability and versatility. The selected chips are suitable for open controller design and have extensive hardware and software resources. Samsung's S3C2410A chip uses an ARM920T core with a clock speed of up to 266MHz. It supports WinCE, Linux, and μC/OS-II real-time operating systems, has a 1GB expandable address space, and is equipped with on-chip peripherals such as interrupts, AD converters, UART, GPIO, a touchscreen, and a TFT interface. Texas Instruments' TMS320F2812DSP chip has a clock speed of 150MHz, supports DSP/BIOS and μC/OS-II real-time operating systems, has a 1MB expandable address space, and is equipped with on-chip peripherals such as interrupts, AD converters, a serial interface, and an event manager. Of these two CPUs, the S3C2410A is mainly used for control system management, monitoring, and the implementation of complex control algorithms, while the DSP is mainly used for servo motor interfaces and the implementation of highly real-time control algorithms such as feedback and filtering. Hardware System Configuration The entire research platform is configured with three motherboards and one backplane, as shown in Figure 3. The three motherboards can be used individually or in combination, providing the S3C2410A hardware platform for MCUs, DSPs, and dual DSPs. The USB ports on the motherboards are for Host, while the USB ports on the other two boards are for Device. Furthermore, the S3C2410A and F2812 motherboards also have serial communication, GPIO, and interrupt communication via the backplane. They can be combined into a two-layer structure with the S3C2410A motherboard as the host computer and the F2812-1 and F2812-2 motherboards as slave computers. The S3C2410A motherboard handles weak real-time tasks, while the DSP handles strong real-time tasks. Weak real-time tasks include system monitoring, complex control algorithms such as fuzzy logic and neural networks, while strong real-time tasks include interpolation calculations, digital filtering, and PID control algorithms. This is used to verify the feasibility of algorithms in the MCU and DSP environments. CPU Expansion and Peripheral Configuration Based on the design requirements of this system, the block diagram of the S3C2410A motherboard is shown in Figure 4. Two HY58V561620CT-H chips are selected to form a 16M×32-bit RAM space; two E28F128J3A150 chips are selected to form a 16M×32-bit Flash space; the XC9536 CPLD is selected for GPIO address decoding and QEP interface implementation; the DAC8534A serial 16-bit DAC is selected to expand the digital-to-analog conversion interface; and the CS8900A Ethernet chip is used to expand the network interface. The F2812-1 motherboard block diagram is shown in Figure 5. It uses an IS61V5126 microcontroller to expand 256K of ROM space, an AM29LV800BT to expand 512K of Flash memory, an XC95144XL for GPIO address decoding, and an AN2131Q for USB device expansion. A 16-bit DAC8534A is added to the McBSP serial port for servo speed and torque control. Notably, the F2812 provides a comprehensive servo motor interface with two event managers. Each event manager includes two general-purpose counters, three compare/PWM units, three capture units, and a QEP channel. The PWM and general-purpose counters work together as the position control mode input for the servo controller, while the QEP channel serves as the position encoder pulse input for the servo motor. The encoder signal from the actuator terminal is extended to the QEP input via a CPLD. Figure 6 shows the block diagram of the F2812-2 motherboard. To verify the parallel control algorithm for multiple motors, two CPUs were connected using a dual-port RAMIDT70V25 on the F2812-1 motherboard, forming a symmetrical structure. Based on the current motor interface configuration on the board, each board can connect two fully closed-loop servo motors, and the F2812-2 motherboard can connect four fully closed-loop servo motors. Conclusion The S3C2410A and F2812 were selected as the embedded hardware research platform for motion control systems, forming a multi-CPU, two-layer controller structure. This structure allows for both independent research on motion control algorithms in single MCU and DSP environments, and research on complex motion control systems in multi-CPU parallel mode. The system is concise, reliable, and conforms to the development direction of open, reconfigurable, and networked motion controllers. The author's innovation lies in designing and implementing an open, reconfigurable, multi-CPU motion controller hardware platform, which can be used for research on complex motion control systems, in response to the development trend of embedded motion controllers.