Furthermore, cost-effective and compact solutions have become possible for low- and medium-power applications. Even more excitingly, as the switching frequency increases to 1MHz, not only are costs further reduced, but smaller inductors and capacitors can also be used. Meanwhile, some new devices have added practical features such as soft-start, current limiting, and PFM or PWM mode selection.
In conclusion, DC-DC converters are undoubtedly the preferred choice for boost applications. However, for buck applications, the choice between DC-DC and LDO requires comprehensive consideration of factors such as cost, efficiency, noise, and performance.
DC-DC converters encompass various circuit types, including boost, buck, buck-boost, and inverting converters. Their significant advantages lie in high efficiency, the ability to output large currents, and low quiescent current. With advancements in integration technology, many new DC-DC converters today require only a few external inductors and filter capacitors to operate. However, it's worth noting that these power controllers exhibit output ripple and switching noise, and their cost is relatively high.
Low-dropout linear regulators (LDOs) are ubiquitous in circuit design. Many have only three terminals: VIN, VOUT, and GND. What could go wrong? Certain LDO design criteria are well-documented, such as the need to observe the correct output capacitor and equivalent series resistance (ESR). Modern LDOs make this much easier, as they support a wide variety of output capacitors, including low-ESR ceramic types. LDO performance metrics such as power supply rejection (PSRR) are also important, as this metric defines the LDO's efficiency in suppressing its input ripple and noise.
Even with a low VIN-VOUT differential, the TPS7A84A low-noise LDO functions correctly. LDO datasheets typically display waveforms of load transient behavior. An example of the TPS7A84A is shown. When reading the datasheet, it's important to pay attention to the test conditions under which the data was acquired. Output capacitance, VIN-VOUT differential, bias voltage, original load current, load current transient, and load transient slew rate are shown. Two curves are displayed, the only difference being the original base load with added load transients. When a load transient is applied, the output voltage drops and recovers because current is drawn from the output capacitor, and it's more difficult to supply the increased load current and return to nominal VOUT for a short period after the LDO's control loop reacts to turn on the pass FET.
The red curve represents a load transient of 3A - 0.5A = 2.5A, and the black curve represents a load transient of 3A - 0.1A = 2.9A. As expected, the black curve shows a deeper drop than the red curve for larger load transients, but both perform very well, with VOUT dropping by only 20-30mV. Interestingly, the overshoot disturbance during load removal step is larger and lasts longer than the disturbance during load application step. The overshoot amplitude increases as the original load current decreases. Typically, when the load is removed, the LDO briefly continues to supply its load current, charging the output capacitor and causing an overshoot. Shortly afterward, the control loop in the LDO reacts by gradually shutting off its pass FET to allow the output to drop to its nominal voltage. Most LDOs cannot actively sink load current; they can only supply it. Therefore, the only thing that discharges the output capacitor to its nominal VOUT is the original load. A 500mA initial load (red curve) will discharge the output capacitor faster than 100mA (black curve), and VOUT will recover to its nominal voltage more quickly.
The lower the initial load, the longer it takes for the LDO to recover its VOUT to its nominal value after the load transient is eliminated. Now, if the load transient is repetitive, such as with certain RF type loads, the results show a 0.56A load being added/removed at a rate of 2kHz to an LDO set to 1.4V o/p. The actual time between the load being removed and then reapplied is 0.4 milliseconds. The first load transient application and removal produces a lower undershoot and overshoot (a drop in VOUT of approximately 8.5mV), but the second, third, and subsequent load transients exhibit worse performance. The drop has worsened to ~112mV, or 8% of VOUT.
Why is this? The reason is that between the first and second load transients applied and removed, VOUT has not yet recovered to its nominal voltage because the original load current discharging the output capacitor is now approximately 0mA. VOUT slowly returns to its nominal voltage. Therefore, the control loop in the LDO is still commanding the pass-FET to be fully off. When the second load transient occurs, the control loop detects that VOUT is dropping and must react in the opposite way to fully turn on its pass-FET to increase the current through it to recharge its output capacitor and support the increased load. This takes time, so VOUT drops more than during the first load transient.
LDOs might be noisier than DC/DC converters!?
Typically, LDOs are used when a quiet power rail is required. Are LDOs noisier than DC/DC converters? Possible use cases. The output noise of an LDO is generated internally and primarily consists of its reference voltage noise. Noise and ripple voltage appearing on the LDO's VIN are suppressed by its PSRR and attenuated on VOUT. As we've seen, load transients can also interfere with the LDO's output voltage, and its control loop is designed to attenuate this. These three sources of noise and ripple also exist in DC/DC converters, and unlike LDOs, they also have switching noise and ripple at their outputs. When a quiet power rail is required, the absence of switching noise and ripple at their outputs often makes LDOs the optimal choice.
For an LDO, the load current at its output is the same as the load current at its input. A 1A load transient disturbance at the LDO output will be reflected as a 1A load transient at its input, and therefore also at the upstream converter powering the LDO. A 1A load transient at the input will disturb the upstream converter powering the LDO—it must also respond to this change in current. This can cause a voltage sag when a load is applied and an overshoot when the load is removed. This noise source at the upstream converter output can easily become the largest noise component in its output, even if it is a DC/DC converter. If the DC/DC converter output also powers other, more sensitive loads, they will be exposed to this ripple voltage, and they may operate with reduced performance. If the LDO is replaced with a DC/DC converter, the input current of the DC/DC converter is its output current multiplied by the duty cycle, D=VOUT/VIN, ignoring losses and averaging over one switching cycle. Therefore, the upstream DC/DC converter powering this DC/DC converter experiences lower load transients at its output, and the upstream DC/DC converter experiences less interference with its VOUT. Thus, the LDO may be noisier than the DC/DC converter itself, but not at its output; rather, it is at the output of the upstream converter powering it.
Thermal effects of LDO on low-noise analog front-end (AFE)
LDOs are typically used to provide a quiet power rail for AFEs. The power dissipation in an LDO is given only by Iout (VIN - VOUT), and the load current is much greater than the LDO's quiescent current. If the load current (Iout) is large and/or the VIN - VOUT difference is significant, the power dissipation can be substantial. As IC packages become increasingly miniaturized, the temperature rise in an LDO can become very significant, leading to hot spots on the printed circuit board (PCB). Heat diffuses from the LDO to the PCB through the ground plane connected to the LDO package's thermal pads. A key performance metric for AFEs is their signal-to-noise ratio (S/N ratio). One component of the noise voltage is the Johnson/Nyquist noise, given by V(rms) = sqrt(4kTBR), where T is the absolute temperature in Kelvin, B is the bandwidth, R is the resistance, and k is the Boltzmann constant. Placing a hot LDO close to an AFE will also increase the AFE's temperature, increase noise, and decrease the S/N ratio, significantly impacting the overall system performance. While placing the LDO close to the AFE is good, it should be avoided to place it too close. For crowded PCBs, consider removing some copper ground planes to prevent heat transfer to the AFE, but do so in moderation so as not to interfere with the ground return current path from the AFE to the LDO.
LDO, or low-dropout linear regulator, stands out for its significant advantages such as low cost, low noise, and low quiescent current. These regulators require simple external components, typically only one or two bypass capacitors. The latest LDO linear regulators have achieved remarkable performance specifications: output noise of only 30μV, PSRR as high as 60dB, quiescent current as low as 6μA, and voltage drop of only 100mV. The key to this superior performance lies in its use of a P-channel MOSFET as the regulating transistor, while traditional linear regulators mostly use PNP transistors.
As a voltage-driven device, the P-channel MOSFET operates without current, significantly reducing its power consumption. In contrast, circuits using PNP transistors require a certain voltage drop between input and output to prevent them from saturating and reducing output capability. The voltage drop of a P-channel MOSFET, however, depends primarily on the product of its output current and on-resistance. Thanks to the MOSFET's extremely low on-resistance, its voltage drop remains very low.
If the input and output voltages are similar, an LDO regulator can achieve high efficiency. For example, in applications where the lithium-ion battery voltage is stepped down to 3V output, an LDO regulator is the preferred choice. Although the last 10% of the battery's energy is not utilized, an LDO regulator can extend battery life while maintaining low noise. However, if the input and output voltages differ significantly, a switching DC-DC converter should be considered. Because the input current of an LDO is usually equal to its output current, an excessive voltage drop will lead to excessive power consumption and reduced efficiency.
