Abstract: Based on the special requirements of oil pipeline data monitoring, this paper designs a data acquisition system based on a distributed structure. The system uses an industrial control computer as the host computer and a DSP signal processing module as the slave computer, realizing real-time monitoring and control of oil pipelines. This paper mainly focuses on the detailed hardware design of the signal processing module in the substation control system. Keywords: pipeline monitoring; signal processing; data acquisition; control module[b][align=center]Design and Realization of Monitoring System for Oil Pipe lines Based on Distributed Structure ZENG Gui e1 Lv Gao Sheng2 Xu Ming3[/align][/b] (1.Electronics DEPT of Guang Dong Baiyun University. Guangzhou 510450, China; 2. Oil & Gas Storage And Transportation Dept of Zhong Yuan Oil Field.Zhengzhou 3. China Petroleum & Chemical Corporation gas company, Jinan, 257010) Abstract: With the special demand of oil pipe lines, design a data acquisition system based on distributed structure. Use industrial data pressing computer as server, and DSP as client. a real-time monitoring system on oil pipe lines is established. this paper is main to design hardware of the signal processing in detail. Key Words: Monitoring Pipelines; Signal Processing; Data Acquisition; Control mode 1. Introduction my country possesses tens of thousands of kilometers of oil pipelines. With the increasing domestic demand for petroleum products and the continuous rise in international oil prices, criminals are increasingly targeting these pipelines, stealing state-owned oil for exorbitant profits. Due to the complex and diverse geographical locations of these pipelines, conventional human-based security measures are insufficient to deter cunning oil thieves. It is essential to utilize modern high-tech methods to establish an accurate and sensitive anti-theft early warning system for oil pipelines. This is crucial to fundamentally improve the security capabilities of the entire oilfield, effectively curb oil theft, reduce losses of state-owned assets, and ensure the oilfield's continued success in the fight against oil theft. This project, undertaken by China Zhongyuan Oilfield Company, is a highly efficient anti-theft early warning system for oil pipelines tailored to my country's national conditions. This paper primarily introduces the hardware system design of the signal processing module. [align=center]Figure 1 System Hardware Composition and Connection Relationships[/align] 2. System Composition The entire intelligent acoustic oil pipeline anti-theft system consists of a substation system distributed at various control points and a main station system located in the oilfield dispatch center, as shown in Figure 1. The main station system consists of an industrial control computer, dedicated main station control software, and a wireless transmission module. The main station control software adopts a master-slave control method to control the entire early warning system, enabling the entire system to operate in an orderly manner. The substation system consists of several parts, including low-power acoustic sensors, filter amplifiers, signal processing modules, wireless transmission modules, power supply systems, and equipment protection systems. The acoustic wave sensor acquires various acoustic wave signals from the pipeline; the filter amplifier filters and amplifies the weak signal output by the acoustic wave sensor; the signal processing module acquires the output signal of the amplifier at high speed, then performs various signal processing operations, and outputs the effective signal to the wireless transmission module through the serial port in the agreed protocol format; the wireless transmission module sends the data back to the main station; the power supply system is responsible for providing the energy required by the entire substation system, and there are solar panels to charge the battery at any time to ensure a long-term energy supply; the equipment protection system protects the entire substation system and makes the substation equipment less likely to be damaged. [align=center] Figure 2 Hardware structure diagram of substation control and processing control system[/align] 3. Hardware design of substation control and processing control system The DSP-based signal processing module [2] consists of an analog-to-digital converter (A/D), a digital signal processor (DSP), an external program memory (FLASH), an external data memory (SDRAM), a reset circuit, a wireless communication control module (UART), a power management module (POWER), and a logic control module (Logic Control). As shown in Figure 2. The A/D module converts the analog signal into a digital signal that the DSP processor can process. The FLASH memory is used to store the fixed digital signal processing program. External data memory overcomes the limitations of on-chip memory space in the DSP. The reset circuit controls the reset timing of the entire circuit, ensuring correct reset of the DSP, A/D converter, and wireless transmission control module in the system. The logic control module receives control signals from the DSP, encodes them, and outputs control signals to the A/D converter, external memory, and wireless transmission control module. The power management module provides a stable power supply for the entire system and a precise voltage reference for the A/D converter. The core processor of the entire system is the DSP, which controls the conversion timing of the A/D converter, receives the digital signal output by the A/D converter, analyzes and processes it to determine if it is a valid signal, and then sends this determination back to the master station via the wireless transmission module. 3.1 JTAG Emulation Port Due to the highly parallel structure, fast instruction cycle, and high-density packaging of high-speed DSPs, reliable simulation using traditional circuit simulation methods is difficult. The TMS320C54X series DSPs use an advanced scanning emulator for hardware simulation of the user board. The scanning emulator does not use the insertion simulation method but instead implements the simulation function through several simulation pins provided on the DSP chip. Scan emulation eliminates the problems inherent in traditional circuit emulation, such as signal distortion caused by excessively long emulation cables and poor reliability due to emulation plugs. User programs can run on-chip or off-chip memory of the target system without introducing additional waiting states due to the emulator. The DSP chip internally implements scan emulation through a shift register scan chain, which is accessed via an external serial port. Using scan emulation, simulation debugging can be performed even if the chip is already soldered onto the circuit board, greatly facilitating the design and debugging of DSP systems. JTAG (Joint Test Action Group) is a boundary-scan test method based on the IEEE 1149.1 standard. TI provides JTAG port support for the vast majority of its DSP products. Combined with the accompanying emulator software, all resources of the DSP, including on-chip registers and all memory, can be accessed, providing a real-time hardware emulation and debugging environment for developers to debug system software. The emulator communicates with the chip's JTAG port via a 14-pin connector. If the distance between the DSPs and the 14-pin connector exceeds 6 feet, a buffer drive needs to be added to the relevant simulation signal. 3.2 A/D Conversion Circuit The preprocessed signal is still an analog signal, while the DSP chip can only process digital signals. Therefore, the A/D converter is a crucial component in the DSP's peripheral circuitry. The selection of the A/D chip directly affects the accuracy of signal measurement and the data capacity; therefore, the design of the A/D conversion circuit mainly involves selecting and applying the A/D chip. Different chips with different performance indicators and price ranges can be selected based on different applications. For general A/D selection, the following factors are mainly considered: 1) Converter accuracy and linearity. 2) Conversion time, sampling rate, aperture time, etc. 3) Logic level requirements of the converter output code; interface with the microprocessor or computer; serial, parallel, and clock selection; output code format, etc. 4) Converter operating conditions, requirements for temperature, humidity, and other natural conditions, as well as shock resistance, etc. 5) The converter's operating voltage, power consumption, packaging form, cost, and availability are also important considerations. Considering various factors, this system adopts a low-power, 12-bit, single-supply high-speed A/D converter (ADC) – MAX144. 3.3 TMS320VC5402 DSP A DSP chip, also known as a digital signal processor, is a microprocessor particularly suitable for real-time digital signal processing. The TMS320C5402 used in this system is a new generation fixed-point digital signal processor launched by TI in 1996. It adopts an advanced modified Harvard architecture, with eight on-chip buses (one program memory bus, three data memory buses, and four address buses), CPU, on-chip memory, and on-chip peripheral circuitry. Combined with a highly specialized instruction set, the C5402 has advantages such as low power consumption and high parallelism, meeting the real-time processing requirements of many fields. The main features of the C5402 are as follows: ● Enhanced Harvard architecture around eight buses; ● Highly parallel CPU design with specialized hardware logic; ● Highly specialized instruction set; ● Modular structure design; ● Advanced IC technology; ● New electrostatic design methods that reduce power consumption and improve nuclear radiation resistance. 3.4 Reset Circuit Design DSPs offer two hardware reset methods: power-on reset and manual reset. The reset input signal for the TMS320VC5402 DSP is the input pin for the hardware reset signal. A low-level input to this pin initializes the DSP's internal logic and wakes up the DSP initialization software. For proper chip initialization, the reset signal must be maintained for at least 5 external clock cycles. However, after power-on, the system's crystal oscillator often requires several hundred milliseconds to stabilize; therefore, the reset circuit should ideally generate a low-level pulse longer than 200ms. Figure 3 below shows the schematic of a composite RC reset circuit combining power-on reset and manual reset. The delay characteristics of the RC circuit are used to provide the required low-level time for reset; the reset time is mainly determined by the product of R and C. The voltage at RS is V = VCC(1 - e^-t/ι), where ι = RC. Let V1 = 1.0V be the boundary between low and high levels, then t = -RC1n(1 - V1/VCC). Choosing R = 100KΩ and C = 10μF, we get t = 223ms, thus meeting the reset requirement. [align=center]Figure 3 DSP Reset Circuit Schematic[/align] 3.5 FLASH MEMORY The TMS320VC5402's on-chip memory includes dual-port random access memory (DARAM) and read-only memory (ROM). DARAM has fast access speed but lacks power-down storage capability; while ROM cannot be repeatedly erased and rewritten by ordinary users, only the chip manufacturer can write data according to user requirements during production. Neither of these two types of memory is suitable for continuous rewriting, and the requirement of power-down data retention is desirable. Therefore, external memory must be added. This system uses the small-sized, high-speed read/write FLASH memory Am29lv800b. 3.6 Clock Circuit The clock generator provides a precise clock signal to the DSP chip. The clock generator consists of an internal oscillator and a phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided in two ways: 1) Connect the crystal across the X1 and X2/CLKIN pins to activate the internal oscillator, forming a feedback circuit. The two capacitors are 22pF. If operating in harmonic mode, additional components are needed. 2) Apply the external clock signal directly to the X2/CLKIN pin. This system uses the first method. 3.7 Power Supply Circuit for the DSP System 1) Power Conversion Circuit The power supply is essential for the normal operation of the DSP chip. The TMS320VC5402 is a low-power, dual-supply circuit. Its peripheral circuits operate at 3.3V, while the core operating voltage is 1.8V. Therefore, voltage conversion is necessary to obtain a suitable power supply voltage. Meanwhile, to reduce the overall system power consumption, the entire circuit uses 3.3V low-power devices. Here, the TPS767D301 linear voltage regulator chip, specifically designed by TI for its DSPs, is used. The TPS767D301 is one of the TPS767D3XX series from TI, primarily used in systems requiring two different voltage power supplies. Depending on the circuit requirements, it can operate in three modes: 3.3V/2.5V, 3.3V/1.8V, and 3.3V/adjustable voltage output. Each output can reach a maximum current of 1A. It features fast dynamic response in power regulation, with voltage adjustment error not exceeding 2% even under overload or high temperature conditions. Voltage stability is excellent, with a voltage drop of only 350mV at 1A current. Each output includes power-on reset and low-voltage monitoring reset functions. It can output a reset signal 200ms after power-on to ensure reliable DSP system reset, and can also monitor the system voltage during operation. When the system voltage drops below a fixed value, it outputs a reset signal to initiate system reset, ensuring reliable system operation. The device's first output voltage is a fixed 3.3V, and the second output voltage is adjustable. V[sub]0[/sub] is the output voltage we need. The formula for calculating V[sub]0[/sub] is: 2) DSP power supply ground jump. DSP chips are high-speed logic circuit chips. From an electromagnetic compatibility perspective, the design has very high requirements for the power supply, and power supply noise and interference should be eliminated as much as possible. In digital signal integrity issues, a very important component is the noise current problem, also known as the ground jump problem. The principle of its generation and interference is: when a digital integrated circuit is powered on, its internal gate circuit will undergo a "0" to "1" transition, which is actually a conversion between high and low output levels. During the conversion process, the transistors in the gate circuit will switch between on and off states, thereby generating a current between the power line and the ground line, which is the source of noise, also known as noise current. Since there is a certain impedance between the power line and the ground line, the change in current will cause voltage spikes through the impedance, and cause fluctuations in the power supply voltage. Because multiple gate circuits share a single power and ground line within an integrated circuit, other gate circuits will be affected by power supply voltage fluctuations. In severe cases, this can cause these gate circuits to malfunction and produce operational errors. This noise current can also be called chip-level noise current. For high-speed chips like DSPs, certain methods must be adopted in the circuit design to suppress this interference. Decoupling techniques in electronic circuit design can prevent noise energy from being transferred from one circuit to another. Using decoupling capacitors in the circuit can compensate for the ΔI noise current generated when logic devices are operating, preventing power supply fluctuations. The calculation method for the local decoupling capacitor is: From ΔI=C(dU/dt), we can obtain C=ΔI/dU/dt. An approximate value of 0.01uf is selected. 3.8 FLASH Memory and DSP Interface Circuit The 16-bit data lines of the FLASH memory are connected to the 16-bit data bus of the DSP parallel interface. The address bus of the memory is connected to the lower 19 bits of the DSP's address bus. The CE# pin of the FLASH memory is connected to the PS pin of the DSP. The OE# pin of the FLASH memory is connected to the R/W pin of the DSP. The WE# pin of the FLASH memory is connected to the R/W signal of the DSP after an inverter. 3.9 Serial Port Control Module: The DSP board communicates with external devices via an RS232 asynchronous serial port. This system uses the TL16C550 serial port control module. The TL16C550 can operate in FIFO mode, in which the internal FIFO can store 16 bytes. To minimize system overhead and maximize system efficiency, all logic is on-chip. The TL16C550 performs serial-to-parallel conversion on data received from peripheral devices (radio) or modems, and parallel-to-serial conversion on data received from the CPU (DSP). The ACE's status can be read or reported at any time during operation. This status includes the type of transmission being performed, the operating status, and any error conditions encountered. The TL16c550 includes a programmable on-chip baud rate generator that can divide the reference clock using divisors from 1 to 65535 to generate a 16× clock to drive the internal transmitter logic. It also includes measures to allow this clock to be directly used to drive the receiver logic. The ACE also includes comprehensive modem control capabilities and an interrupt handling system to meet customer requirements for minimizing the software management workload of the communication link. 3.10 Signal Detection and Analysis Workflow The A/D converter converts the analog signal output from the filter amplifier into a digital signal. The data is sent to the DSP's on-chip memory via DMA. The DSP reads the data from the memory and performs various calculations. If data needs to be transmitted after calculation, the data to be transmitted is output to the wireless transmission module through the serial port control module according to the agreed protocol, and then sent back to the master station by the wireless transmission module. The power management module provides a stable and reliable power supply for the entire signal processing module; the logic control module facilitates DSP management of each module; and the reset module can automatically provide a reset signal and restart the entire substation system when an anomaly occurs in the entire signal processing module. 4. Conclusion This system utilizes a high-speed, low-power DSP (Digital Signal Processor) for sound signal analysis and processing. It can complete complex mathematical calculations with lower power consumption and faster speed. Furthermore, its powerful computing capabilities give the system great potential for development in processing algorithms and functional expansion, ensuring strong system upgrade capabilities from a hardware perspective. The current sensor detection distance is 1km. To enable the intelligent acoustic detection system to be applied in a wider range and further reduce system costs, it is considered to install the sensor inside the oil pipeline to receive the acoustic signal propagating through the liquid inside the pipe. This would increase the sensor's detection distance and reduce external noise interference with the target signal. Experiments show that the existing early warning judgment method is effective. However, for potential new problems, we still need to further improve the signal processing algorithm, target recognition algorithm, and main station program functions to adapt to the requirements of new applications. References: 1. Sun Junruo, Hu Guichi. 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