Introduction Currently, the design of 1553B bus interface boards in China is generally based on the DDC BU-61580 protocol chip, but this only handles the protocol processing. External memory and microprocessors are still required for application. Therefore, a Field-Programmable Gate Array (FPGA) is used to implement the core design of the entire interface board. 1 System Overall Architecture After the 1553B bus signal enters the interface board, it is first converted by an isolation transformer to match the operating voltage of the transceiver. The transceiver then converts the 1553B differential signal into a recognizable TTL level. However, the signal is still Manchester Type II code at this point, so it needs to be decoded and converted from serial to parallel. Simultaneously, data word synchronization, data and Manchester code error detection, parity detection, and bit/word counting are performed. After processing, the serial-to-parallel converted data is stored in memory for further protocol processing. When sending data, the data received by the terminal is temporarily stored in memory, awaiting the transmission command. Once a send command is received, data is sent, converted from parallel to serial, then encoded in Manchester, modulated, and demodulated before being sent to the dual-redundant bus of the 1553B. See Figure 1.2 for system hardware configuration and implementation . The signal modulation and demodulation uses isolation transformers and transceivers, employing HOLT's PM-DB2725EX and HI-1570 chips respectively. The Manchester encoding/decoding portion can be implemented within a single FPGA chip, with Altera's Cyclone series EP1C12 selected as the main chip. The circuitry for the FPGA-bus interface is shown in Figure 2. 3. FPGA Internal Module Configuration and Implementation. The FPGA implementation is accomplished through Verilog programs and calls to Quartus II software macro modules, and can be divided into dual-redundant Manchester II encoding/decoding and serial-to-parallel conversion modules, bus transmission logic, terminal protocol and message processing, memory, controller, and subsystems. 3.1 Dual-Redundant Manchester II Encoding/Decoding and Serial-to-Parallel Conversion Module. This module implements Manchester code encoding/decoding, and after serial-to-parallel conversion, communicates with the bus transmission logic module. The raw data sampling uses a 16MHz clock frequency. 3.2 Bus Transmission Logic Module: This module decomposes and stores the 16-bit parallel data from the previous module according to the 1553B protocol definition, and provides response signals and command execution to the protocol module, issuing corresponding status words and data words. 3.3 Memory and Controller Module: This module serves as the system register and data storage area for data exchange with lower-level subsystems, responding to potential register and data access from other modules. This module consists of the following three sub-modules: DPSRAM Module: This is the instantiation call of the Quartus software macro module altsyncram, physically representing the call to the FPGA chip's on-chip SRAM. After instantiation, it becomes a dual-port synchronous SRAM memory that can be read and written simultaneously, satisfying potential access requests from the bus transmission logic, protocol processing module, one of the initialization self-test modules, and subsystem modules. RAM_Control Module: This is the memory controller for the previous module's DPSRAM, generating read/write enable, address, data, and read/write confirmation signals conforming to the DPSRAM timing based on signals from the upstream (user_interface module). The `user_interface` module resolves the issue of multi-port inputs not being able to directly wire-AND and directional outputs being able to read data from the DPSRAM. 3.4 Terminal Protocol and Message Processing Module: This module parses received commands and notifies the bus transmission module to respond accordingly. It can be divided into the following four sub-modules: ① The `read` module reads the instruction word; ② The `protocol` module analyzes the instruction word and processes the protocol; ③ The `write` module modifies the corresponding status word based on the instructions sent after the `protocol` module parses the command; ④ The `choose` module selects the commands and addresses sent to the RAM by the `read` and `write` modules. 3.5 Subsystem Modules: The subsystem includes modules for transceiver, terminal address generation, and verification. ① Transceiver Module: Converts 16-bit parallel data to 2400-bit serial data in memory; ② Terminal Address Generation and Verification Module: The terminal address is set by the subsystem's DIP switch. It reads the DIP switch's level value, generates the corresponding parity bit, stores it in the terminal address register in memory, and initializes the status word. When writing the code for the above modules, the state machine transition condition was originally based on detecting the level value. However, during simulation, it was found that sometimes the level value could not be detected or was detected multiple times, leading to malfunctions in the state machine. The problem was solved by using the following edge detection method, and the corresponding code is as follows: The principle is: the signal to be detected is continuously latched twice by two D flip-flops. The action is only executed when the value of the two latches meets the edge detection condition, as shown in Figure 3. After adopting this detection method, the program simulation does not have similar instability problems, but it also causes an additional delay of one clock cycle. 3.6 Simulation and FPGA Implementation The above functional modules are written in Verilog, and the memory is called by Quartus II macro modules. The entire program's functional simulation, synthesis and routing, and final timing simulation are all completed using ALTERA's Quartus II. After synthesis, each module is compiled in Quartus II to generate a symbol, as shown in Figure 4. Figure 5 shows the simulated waveform of a certain type of tuned filter communicating with the 1553 bus. The RT address is set to 00101, which corresponds to the level values ​​of DIP switches pat4 to pat0 in Figure 4, with a sub-address of 00001. After reset, the first message is the vector word mode command and its response when the RT does not send a data request; the data word in the status word is &H0000. This command is sent to the RT cyclically until a request is received (the third message). The second message is the RT receiving a one-data-word command and its response. The third message is the vector word sent and its response when the RT requests data; the data word in the status word is &H0001. The fourth message is the RT sending two data-word commands and their responses. The fifth message is the synchronous mode command with data words and its response. As can be seen from the simulation waveforms, the system basically meets the application requirements of the filter. To further verify its practical application and other protocols, it was downloaded to an FPGA for testing. Since the FPGA is based on an SRAM structure, a configuration chip is needed to solidify its internal structure; therefore, two configuration modes are used: JTAG mode and Active Serial (AS). During debugging, the logic was directly written into the FPGA using JTAG mode. After debugging, the program was written into the configuration chip EPCS4 using AS mode, and the test was successful. 4. Conclusion The FPGA-based bus interface board design has passed testing on a military aircraft, realizing communication between the 1553 bus and subsystems. Applying FPGA technology to the 1553B bus interface reduces design costs, shortens the design cycle, improves system integration, and enhances scalability, possessing significant practical value and application prospects.