Abstract: This paper first describes the development and hierarchical structure of the HART communication protocol. Based on the design and implementation requirements of a HART protocol remote communication module for a field instrument, the hardware and software design of a HART protocol communication module based on the HART modem A5191HRT and current loop digital-to-analog converter AD421 was completed. Keywords: HART protocol; serial communication; frequency shift keying Introduction : The HART (Highway Addressable Remote Transducer) communication protocol was introduced by Rosemount Corporation in the mid-1980s. It has since been revised and supplemented, and as an open standard, it was released worldwide by the HART Communication Foundation (HCF). It is mainly used for digital communication between field intelligent instruments and control room systems. Due to its compatibility with traditional 4-20mA analog systems, the HART communication protocol has many advantages and has been adopted by more than two-thirds of field devices worldwide, becoming a de facto international standard in the field of intelligent industrial control. In the development of a certain intelligent field instrument, a HART protocol remote communication module was designed and implemented using a single-chip HART modem A5191HRT and a digital-to-analog converter AD421. This module boasts advantages such as high precision, low power consumption, low cost, and high reliability. HART Protocol Introduction : The HART protocol is a transitional fieldbus standard compatible with existing 4-20mA analog systems. It features bidirectional digital communication by superimposing digital signals onto 4-20mA analog signals, ensuring compatibility with existing analog systems; simultaneous point-to-point 4-20mA analog and digital communication; multi-station communication; transmission of various information such as measured variables, device settings, and device test results; an open architecture, freely available to any manufacturer and user; and a digital response time of 500ms and a burst mode time of 300ms. The HART protocol references the ISO/OSI model, employing its simplified three-layer structure, including the physical layer (layer 1), data link layer (layer 2), and application layer (layer 7). The physical layer specifies the signal transmission method and medium. To enable simultaneous analog and digital communication without interference, the HART protocol employs FSK (Frequency Shift Keying) signals based on the Bell202 standard. Audio digital signals are superimposed on low-frequency 4–20mA analog signals for bidirectional digital communication. The audio digital signal amplitude is 0.5mA, the data transmission rate is 1200bps, 1200Hz represents logic "1", and 2200Hz represents logic "0", as shown in Figure 1. Since the average value of the FSK signal is 0, it does not affect the magnitude of the analog signal transmitted to the control system, ensuring compatibility with existing analog systems. Figure 2 shows a schematic diagram of the simultaneous transmission of superimposed digital and analog signals in the HART protocol. The choice of communication medium depends on the transmission distance; when using twisted-pair cable, the maximum transmission distance can reach 1500m, and the total line impedance should be between 230 and 1100Ω. The data link layer defines the format of the HART protocol frames and implements the functions of establishing, maintaining, and terminating link communication. The HART protocol uses an automatic repeat request mechanism based on redundant error detection code information to eliminate data errors caused by line noise or other interference, achieving error-free data transmission. The format of the HART protocol information frame is shown in Table 1. For field instruments to execute HART commands, the operands must conform to the specified size. Each independent character includes: 1 start bit, 8 data bits, 1 parity bit, and 1 stop bit. Because the presence and length of data are not constant, the length of HART data also varies, with the longest HART data containing 25 bytes. The application layer is the HART command set, used to implement HART commands. Commands are divided into three categories: general commands, ordinary commands, and special commands. In HART protocol communication, the main variables or control information are generally transmitted via 4–20mA, while many other measurement data, equipment parameters, calibration information, diagnostic information, etc., are transmitted through the HART protocol using half-duplex communication. Hardware Design of HART Protocol Communication Module A certain intelligent field instrument requires the transmission of its most important measurement result using a traditional 4-20mA signal. It then uses HART protocol digital communication to exchange instrument setting parameters, intermediate measurement data, calibration parameters, and other information with control equipment. Therefore, the HART protocol communication module needs to perform the DA conversion from the digital code of the measurement result to a 4-20mA analog signal, as well as the HART protocol digital communication of the aforementioned information. The block diagram of the completed HART communication module is shown in Figure 3. The HART protocol communication module is mainly implemented by a HART modem A5191HRT and a D/A converter AD421 and their peripheral circuitry. The AD421 receives the digital signal transmitted from the field instrument's internal MCU through a serial interface, converts it into a 4-20mA current output, and outputs the main measurement result. The A5191HRT receives the signal superimposed on the 4-20mA loop, performs bandpass filtering and amplification, and then performs carrier detection. If an FSK (Frequency Shift Keying) signal is detected, the 1200Hz signal is demodulated to "1" and the 2200Hz signal is demodulated to "0", and transmitted to the MCU via serial communication. The MCU receives the command frame and performs corresponding data processing. Then, the MCU generates an acknowledgment frame to send back. The digital signal of the acknowledgment frame is modulated by the A5191HRT into corresponding 1200Hz and 2200Hz FSK signals, and after waveform shaping by the transmit signal shaping circuit, it is superimposed on the loop by the AD421 and transmitted. The A5191HRT is a single-chip HART modem from AMI Semiconductor, using a phase-continuous FSK half-duplex operating mode with a data rate of 1200bps. The A5191HRT integrates a Bell202 compliant modulator, demodulator, receive filter, transmit signal shaping circuit, carrier detection circuit, and other circuits, operating at a current of 330μA with a +3.3V power supply. These features allow designers to build circuits that meet the physical layer requirements of the HART protocol with fewer external passive components. In this design, when the A5191HRT receives signals from the 4–20mA loop, it performs bandpass filtering, amplification, and shaping to extract the FSK signal, demodulates it into a digital signal, and transmits it to the MCU. During transmission, it receives data from the MCU, modulates and shapes the waveform, and couples it to the AD421, which then superimposes it onto the loop. The A5191HRT and the MCU are connected via the latter's universal serial communication interface. The AD421 is a high-performance monolithic digital-to-analog converter from Analog Devices (ADI), primarily composed of a voltage regulator, a digital-to-analog converter, and a current amplifier. The voltage regulator, consisting of an operational amplifier, a bandgap reference, and an external FET regulator, draws current from the loop to provide a selectable supply voltage of 3.0V, 3.3V, or 5.0V for the AD421 and other devices. The digital-to-analog converter (DAC) employs a Σ-ΔDAC structure, converting 16-bit digital code into a 4–20mA analog current. The digital code is serially input from the MCU via a three-wire interface (CLOCK, DATA, and LATCH). The schematic diagram of the A5191HRT and its peripheral circuitry is shown in Figure 4. The interface signals with the MCU's Universal Serial Transceiver (UART) module include Carrier Detection (OCD), HART Demodulation Output (ORXD), HART Modulation Input (ITXD) from the UART, and Request to Transmit (INRTS). Loop+ is a 4-20mA loop input, which, after passing through external resistors and capacitors and the internal circuitry of the A5191HRT, undergoes bandpass filtering and amplification for demodulation. The modulated data, after being processed by the internal shaping circuit, is output from pin OTXA, coupled to the AD421 via a capacitor, and then superimposed onto the loop for transmission. The clock signal for HART modulation and demodulation originates from the oscillation generated by an external 460.8kHz crystal. The schematic diagram of the AD421 and its peripheral circuits is shown in Figure 5. Loop+ and Loop- are the two ports of the current loop. The digital code input from the MCU to the DAC is implemented through a three-wire interface: clock line (CLOCK), data line (DATA), and latch line (LATCH). The software design of the HART protocol communication module includes the control of the AD421 and the software program design of the HART communication protocol. The former is simpler, while the latter includes the software design of the HART protocol data link layer and application layer, and is the main body and key of the entire module's software design. The communication process of the HART protocol communication module is initiated by the host (upper computer) sending a command frame. The field instrument, as a slave device, uses interrupt calls to subroutines to complete the reception and response. After the field instrument is powered on or the watchdog is reset, the main program first initializes the HART protocol communication module, such as setting the UART operating mode, serial communication baud rate, data frame format, clearing the communication buffer, and enabling interrupts, and then sets it to a waiting state. When the host computer sends a command, the carrier detection output OCD of the A5191HRT goes low, triggering a UART interrupt, and the program enters the reception process. After the MCU completes the reception, interpretation, and execution of the host command, it generates a response frame in a certain format and sends it to the transmission buffer. After transmission is completed, the HART protocol communication module is set to a waiting state again. Figure 6 is a flowchart of the program for the HART protocol communication module to receive host frames and reply with response frames. The HART protocol communication module, through the interrupt call subroutine method shown in the diagram above, completes communication between the field instruments and the host computer. This allows the host computer to perform tasks such as setting operating parameters, reading measurement results, and instrument testing for the field instruments. Conclusion Practice has proven that the implementation method of the HART protocol communication module described above is feasible, possessing advantages such as simple circuit design and high reliability. It has significant reference value and practicality. HART technology is already mature abroad and, due to its outstanding advantages, has become the most widely used field communication protocol in the field of intelligent control. For a considerable period to come, HART technology will play a vital role in the intelligent transformation and development of field instruments in China. References: 1. HCF. Hart Field Communications Protocol Application Guide. 1999. 2. Smar International Corp. HART Technology Guide. 3. Zhang Shi, Cai Huilong. HART Field Communication Protocol: Principles and Applications. Measurement and Control Technology. 1999.2. 4. Xin Changyu, Lü Xiujiang. Interface between AD421 and HART Modem 20C51. Electronic Products World. 2001.9. 5. Wang Hongchang, Li Baokang. Characteristics and Progress of HART Technology. Automation and Instrumentation. 2002.