Introduction In recent years, PC technology has increasingly penetrated the embedded application field. Embedded PCs, with their ultra-small size, extremely low power consumption and heat dissipation, and the ability to be directly stacked and combined into various systems without a chassis or baseboard, have gained popularity among users and thus possess enormous application potential. Early embedded PC products were based on standardized motherboards using 8-bit and 16-bit ISA buses. Later, various miniaturized embedded PC products were developed. Currently, among the most representative miniaturized embedded PC products internationally, the PC104 stands out. Measuring only 9.14cm × 9.65cm, it eliminates the need for plug-in boards and bus motherboards, employing a stacked packaging method between modules. The PC104 is fully compatible with the ISA standard. Therefore, users can fully utilize the widely accepted PC architecture and existing hardware and software resources to combine more functions to meet their needs, developing new PC104 products that significantly shorten product development cycles and reduce costs. With the development of information network technology, there is often a large demand for network connectivity in industrial applications. Currently, to achieve networked systems, industrial equipment must appear in the system as network terminals. Due to the diversity and distribution of industrial control system equipment, embedded terminals using intelligent modules have become the mainstream equipment control method, and these network terminals are mostly implemented using microcontrollers or digital signal processors. In cases of simple functionality and low performance requirements, 8-bit or 16-bit MCUs often meet the field requirements. With the reduction in hardware costs and the increasing demand for higher power, more complex, and feature-rich embedded applications, 32-bit machines have seen significant growth in the high-end embedded processor market. Typical examples include the ARM series from Advanced RISC Machines, the PowerPC from IBM and Motorola, and the MIPS chips from Silicon Graphics. Intel has also added a dedicated product series, the 386EX, to its existing x86 series, with software fully consistent with other x86 microprocessors. Based on this, this paper proposes a method for designing the NP104 intelligent Ethernet expansion module using the Intel 386EX embedded microprocessor. This module can meet the need for fast internet access for intelligent electronic devices based on PC104 or industrial PCs in industrial field applications. 1. Basic Composition and Functional Overview The NP104 is an intelligent Ethernet expansion module supporting the PC104 bus. The NP104 occupies approximately 4KB of memory space on the PC104 bus (or ISA bus) and exchanges data with the main system via high-speed dual-port RAM. The main functions of the NP104 intelligent network expansion module include: receiving data submitted by the system CPU in real time, encapsulating it according to the TCP/IP protocol, and sending it to the destination through the board's Ethernet control interface; automatically receiving data sent from the network, unpacking it to obtain application data, and storing it in the dual-port RAM for the system CPU to read. The NP104 is primarily designed for intelligent electronic devices based on PC104 or industrial PCs, and for applications requiring rapid device networking. Because it exchanges data with the system CPU via dual-port RAM, customers only need to add one NP104 board to their existing equipment and add a few lines of simple code to the program to achieve data transmission over the network, minimizing the time-to-market for new products. In addition, the NP104 supports the DOC2000 large-capacity electronic disk, enabling advanced network applications such as embedded web servers. Figure 1 is a hardware functional block diagram of the NP104. As shown in Figure 1, the NP104 is a complete embedded system based on the Intel 386EX, with the following main technical specifications: * It uses only the XT bus portion of the PC104, making it compatible with all PC104 motherboards or industrial PC motherboards with PC104 interfaces; * The system CPU's read/write speed to the dual-port RAM on the NP104 is no less than 500 KB/s, ensuring that the PC104's read/write speed does not affect network transmission speed; * The 386EX on the NP104 operates at a clock speed of 40MHz, with a typical instruction cycle of 100ns, meeting the needs of most applications; * Standard 10Mbps Ethernet interface, 10Base-T connection; * Configurable memory space occupied by the dual-port RAM; * Utilizes the PC104's IRQ5 interrupt resources for rapid response to communication requests; * Standard PC104 board size (96mm × 90mm). The main internal technical specifications of the NP104 are as follows: * 48MHz Intel386EX high-performance, 32-bit microprocessor; * 512KB Flash memory with disk file driver software interface; * 10Base-T Ethernet control interface, NE2000 compatible; * One standard RS232C serial port (9 wires); * Directly supports M-System's DiskOnChip2000 series high-capacity electronic disk chips; * Power supply voltage: 5 (1±0.05)V, operating current 570mA; * Standard PC104 size: 96mm×90mm, with standard mounting holes; * Operating temperature: -10～65℃, operating humidity: 5%～95%, meeting the damp heat test requirements for electronic products specified in Chapter 21 of international GB7261; * The NP104 ensures that it does not affect the image interference test specified in GB6162 and the parameter-level fast transient interference test specified in international GB/T14598.10 of the embedded whole device. 2. System Design Description The NP104 is an embedded system based on the 386EX core, exchanging data with the PC104 main CPU via dual-port RAM. Hereinafter, the CPU within the NP104 expansion board is referred to as the 386EX, and the system CPU on the PC104 is referred to as the main CPU. As a 10 Mbps Ethernet interface, an 8-bit data bus width is sufficient to meet application requirements. The dual-port RAM device selected is the 4K×8bit IDT7134LA, packaged in a PLCC52. The dual-port RAM data area is defined as shown in Table 1. As can be seen from Table 1, the dual-port RAM is divided into two basic parts: one corresponding to the main CPU reading application data from the network from the NP104 board, and the other corresponding to the main CPU writing application data into the NP104 buffer, where the NP104 performs corresponding operations according to commands. The functional definition of each data segment is described in detail below. Table 1 (1) Initialization process The main CPU initializes the input buffer in the following order: ① Clear the input data packet ready status byte; ② Clear the semaphore byte, i.e., idle; ③ Enable the device interrupt as needed; ④ Set the initialization status to 0x12345678. The 386EX initializes the output buffer in the following order: ① Clear the output data packet ready status byte; ② Clear the semaphore byte, i.e., idle; ③ Enable the device interrupt as needed; ④ Set the initialization status to 0x12345678. (2) Definition and operation of semaphores and status bytes In order to ensure that both CPUs can play their full role, the data communication between the dual-port RAMs on the NP104 board does not use the blocking handshake line method, but uses the non-blocking semaphore communication method. The basic operating principle is: when the CPU wants to read or write data in a certain buffer, it must first check the corresponding semaphore byte. If the semaphore is idle, then set the semaphore to busy. After that, the corresponding buffer can be operated. After the operation is completed, the semaphore is set to idle. If it is just a query of the status, there is no need to operate the semaphore. The prerequisite for performing any operation on the buffer is that the initialization status word (long integer) of the buffer has been set to 0x12345678. (3) Data communication process between the main CPU and 386EX During the communication process between the main CPU and NP104 of the PC104 system, the main CPU and 386EX perform data transmission and reception through dual-port RAM. When the system CPU writes data to the output buffer, the 386EX reads data from the output buffer. Correspondingly, the 386EX receives data from the network and writes it into the input buffer. Then, the system CPU reads data from the input buffer. Here, the input and output buffers are relative to the main CPU of the system. (4) Interrupt enable byte and use of NP104 card to support the main CPU to read data from the input buffer in interrupt mode. Before that, the main CPU needs to set the corresponding interrupt enable bit to 1. When the 386EX sets RcvDatRdy to 1, the NP104 card has a dedicated hardware logic to detect this operation, thus setting the interrupt request line IRQ# for the main CPU to 1; when the main CPU clears RcvDatRdy to 0, the NP104 card will reset the interrupt request line IRQ# to 0. Correspondingly, the 386EX can also use interrupt mode to read data from the output buffer, before which the 386EX needs to set the corresponding interrupt enable bit to 1. When the main CPU sets SndDatRdy to 1, the NP104 card has a dedicated hardware logic to detect this operation and sets the interrupt request line INT3 (IRQ7) for the 386EX to 1; when the 386EX clears SndDatRdy to 0, the NP104 card will reset the interrupt request line INT3 to 0. (5) Resource Allocation Description: The dual-port RAM is mapped to the storage space area A8000H～A8FFFH in the 386EX; the dual-port RAM is mapped to the space area D8000H～D8FFFH in the PC104; the page address register port address of the 512K electronic disk is 0X300H. 3 Module Driver Design and Testing The typical development method for embedded application software is the "host/target machine" approach. First, the abundant resources and good development environment on the host machine are used to develop and simulate the software on the target machine. Then, the cross-compiled target code is transmitted and loaded onto the target machine via the serial port or network. Finally, the target machine runs in a specific environment. The PC104 requires driver support to function properly. This driver is written in ANSI C language. Due to the PC-compatible program runtime environment, the existing inexpensive software resources on the PC can be fully utilized without the need for a dedicated development and debugging system. The program is implemented in the Borland C3.0 integrated development environment. Through the link with the encapsulated TCP/IP protocol stack, the NP104 provides a driver for the dual-port RAM. The driver program is generated as an .EXE file by compiling and linking a project file containing several source files to the TCP/IP protocol stack. This file is then remotely downloaded to the electronic disk of the NP104 hardware system via BC. The system BIOS calls this .EXE file. Once the embedded expansion module's device is running normally, the system possesses network communication capabilities. Its basic program flowchart is shown in Figure 2. As can be seen, under normal system operation, the NP104 continuously checks the Ethernet and responds to interrupt commands from the host system to ensure normal communication between the host system device and the network. Correspondingly, for the host system, the NP104 interface driver includes 12 function calls: dual-port RAM initialization, Ethernet interface initialization, establishing and closing TCP connections, reading TCP/IP network interface data, and sending data to the TCP/IP network interface. The software in this system runs on a DOS-based operating system. Additionally, this system can also provide an application environment based on multi-tasking RTOS such as VRTX and DeltaOS. During system testing, the NP104 and PC104 motherboard constitute the basic environment. The NP104 is connected to the local area network (LAN), and the test program on the PC104 motherboard (written using BC) communicates with the host computer on the LAN by calling the NP104 interface program. Simultaneously, a host PC is connected to the LAN, and a corresponding test program (written using VC) runs to verify the NP104's communication function. During system testing, various possible abnormal situations during communication were considered as much as possible, and corresponding handling measures were taken. For example, if the NP104 malfunctions and restarts after an abnormal operation, the PC104 can promptly detect the NP104's reset information. Additionally, if the PC104 host experiences an abnormal restart, the InitNP104() function can be used to restart the NP104. This function implements a hardware reset through software to ensure normal NP104 communication. Conclusion The intelligent network expansion module based on the PC104 bus, designed using the Intel 386EX embedded microprocessor, can meet the high-speed internet access requirements of intelligent electronic devices based on the PC104 bus or industrial PCs. In field applications at the China Electric Power Research Institute's Power Electronics Company, the module designed using this method has been running normally. With the increasing prevalence of embedded applications, the demands for high performance and real-time performance in various field applications are constantly increasing. RTOS will dominate embedded system design, and embedded Linux will be increasingly widely used in embedded systems. Products based on PowerPC, MIPS, and StrongARM microprocessors will continue to appear in future field applications.