Local Controller Network (CAN) has been widely used in industrial distributed control systems due to its low cost and high reliability. The low cost and easy configuration of Ethernet have also made it widely used in computer communication networks. This paper introduces the development of an integrated communication gateway system based on Ethernet and Controller Area Network bus communication system. The purpose of the system development is to exchange real-time control information between Ethernet and Controller Area Network bus to realize distributed control and monitoring. 1 Hardware Platform Design One of the biggest challenges in the design of embedded processor programmable logic circuits is to suit applications with very wide speed requirements. At the low end, the system requirement may be less than 10 MIPS; at the high end, the system may require several hundred MIPS. Different systems require different ranges. A solution that fully meets the range requirements needs to provide programmable device configuration, operation and users who are proficient in embedded processors. The gateway system design is based on the Altera Excalibur[3] embedded processor, which can provide the best solution with better adaptability and powerful performance. The design structure of the ARM system based on the core part SOPC[4] is shown in Figure 1. The controller gateway structure is shown in Figure 2. 1.1 Design of Soft-core CAN Controller The Soft CAN controller using the AMBA bus interface is designed and developed for controller network communication and can run on the gateway system platform. The Soft CAN controller has all the protocol functions of the CAN 2.0B[1] specification, including error handling capability, padding bit generation, cyclic redundancy check (CRC), active/passive error frame and extended frame technology support. The Soft CAN controller can also support the following application developments: information filtering, information encapsulation, information transmission buffer, information reception buffer and interrupt triggering of transmission, reception and error events. The Soft CAN controller provides an AMBA compatible interface to realize high-speed data transmission and also provides interrupt support to realize fast system response. 1.2 Simulation and Verification of Soft CAN Controller The simulation and verification platform design of the Soft CAN controller is shown in Figure 3. The comprehensive simulation/verification output waveform of the Soft CAN controller (Figure 4) shows that its controller is working correctly. From the verification output results shown in Figure 4, the following conclusions can be drawn: (1) Soft CAN controller #1 status: “00000000000000000000000000001000” ——> The Soft CAN controller is controlling the CAN data line signal. (2) Soft CAN controller #2 status: “0000000000000000000000000001000” ——> The Soft CAN controller is controlling the CAN data line signal. (3) Soft CAN controller #1 TX buffer: Identifier - “11101101000”, Data - “100110011001100110011001100110011001”. (4) Soft CAN controller #1 TX buffer: Identifier - NA, Data - NA. 2 Software Design Software design includes real-time operating system[5] porting, exception handling support, device driver development and file system development. 2.1 Real-time Operating System Porting eCos was successfully ported to the gateway system hardware platform to provide real-time services for the development of application systems. Due to the layered structure of eCos, its porting is flexible and easy. The absolute code of all structures and platforms is implemented in the Hardware Abstraction Layer (HAL). 2.1.1 System Boot Modes This system porting provides four boot modes. (1) ROM boot mode. In ROM boot mode, the application is stored in the flash memory of the EPXA1 development board and is started from there. (2) ROM-RAM boot mode. In ROM-RAM boot mode, the application is stored in the flash memory. The boot program will run from the flash memory first and initialize the system. After the system is initialized, the eCos application will be automatically copied from the flash memory to the SDRAM and then run at a higher speed in the SDRAM. (3) RAM boot mode. In RAM boot mode, the eCos application is launched via a debugger on the EPXA1 board (e.g., RedBoot loaded into the board's SDRAM memory). This is primarily for debugging. 2.1.2 Thread Management The EPXA1 eCos port fully supports multi-threaded programming. In addition to task synchronization support, it provides a range of selectable scheduling algorithms. 2.1.3 System Timing Support The system's timing base is provided by the system timer on the Altera EPXA1 platform, with a timer frequency of 150MHz. The system pulse period is 10 milliseconds. The eCos control ported on EPXA1 provides pause, delay, and scheduling services through a clock or timing device used by the kernel for the system kernel's use. 2.2 Exception Handling All exceptions, including FIQ and IRQ interrupts [7], jump to vector 0 address, with each interrupt vector occupying 4 bytes. There is only one instruction space here, which must immediately jump to code at a higher address in memory. The interrupt source must be decoded. Since each vector service routine corresponds to a different CPU mode entry, a different VSR is needed for each exception, which knows how to completely and correctly save the CPU state from the interrupt controller. This exception handling mechanism includes a separate interrupt handling scheme. In this scheme, interrupt handling is divided into two parts. The first part is called the Interrupt Service Routine or ISR; the second part is the Delayed Service Routine or DSR. This division clearly takes into account that DSRs run concurrently with the interrupts being executed, thus allowing other interrupts with higher priority to occur and be handled when a lower-priority interrupt is being executed. 2.3 Device Driver Development 2.3.1 Flash Device Driver This project developed a driver based on Intel 28F320C flash memory. The boot-loader uses it to store the image, configuration information, and data in the flash memory. This device driver provides extensive operational support. (1) Flash Query: The manufacturer and part number codes can be retrieved from the flash memory. (2) Flash Block Erase: The module in the flash memory is erased. (3) Flash Programming Buffer: Allows buffered data to be written to the flash memory. (4) Flash Segment Lock/Unlock: Allows the contents of the flash memory to be protected. 2.3.2 Ethernet Interface Device Driver The Ethernet device driver supports the SMC91C111 Ethernet controller, which can provide dual-speed 10/100Mbps communication support. The Ethernet device Lan91C111 provides all the necessary functions such as sending, receiving and event interruption to support integration with the BSD TCP/IP stack to implement the TCP/IP network protocol. 2.3.3 Soft CAN Controller Device Driver This device driver provides support for controller area network communication to implement sending, receiving and interrupt handling functions. Figure 5 is the driver flowchart. 2.4 Embedded File System Development In order to make information storage and exchange more efficient, this project developed a file system based on flash memory and RAM. The file system provides extensive file operation support: file creation, file deletion, file copying, file renaming and file moving, as well as directory support. The file system can be cross-operated, and files can be copied or moved between the file system-based flash memory and RAM. 2.5 Debugging Support Generally, hardware simulation methods require a lot of money. In order to achieve low-cost design, a software-based debugging method was adopted. The software-based EPXA1 platform debugging tool has been integrated into the gateway platform to provide debugging functions in system development. The debugger can use a serial port or Ethernet channel to communicate with the host. The software debugger provides general debugging functions such as single-step operation, variable access, processor register recovery, resource level debugging and breakpoint support. 3 System Integration 3.1 Application of Network Real-time Welding Control System This application provides a distributed network solution to monitor a distributed real-time welding control network. Users can monitor the SMD[8] positioning welding control network via the Internet. The SMD positioning welding system is shown in Figure 6. The application system is based on the support of an embedded network server to dynamically generate the required web pages for remote computers, i.e. monitoring and configuration. 3.2 System Verification and Conclusion The real-time performance of the gateway system can be evaluated by running related tasks using instruments. The data collected from the entire set of experimental operations were analyzed to obtain the average, maximum and minimum values; the sample variance was calculated; the time required to obtain the real-time clock value was measured and other times were subtracted. The obtained data shows that... To ensure that the monitoring system's webpage does not lose any controller area network (CLAN) information, the following receiving timing measurement method has been adopted: the controller network communication speed of the network monitoring system is 125Kbps, the system operating frequency is 75MHz, and the CLAN standard limits the minimum inter-frame interval to 3 bits. Therefore, in a fully loaded controller network, the idle time between CLAN information frames can be calculated using equation (1): From the results displayed by the real-time characteristics of eCos, the interrupt response time is 5.31 microseconds. Therefore, the timing result can be obtained from equation (2). Through the above verification, it is known that the network monitoring system webpage can monitor the SMD positioning welding control network, and will not lose any real-time monitoring information even when the network bus is fully loaded.